### Fewer G^{4}FETs than conventional transistors would be needed to implement logic functions.

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G^{4}FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G^{4}FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors.

^{4}FETs as Universal and Programmable Logic Gates” (NPO-41698)

*NASA Tech Briefs*, Vol. 31, No. 7 (July 2007), page 44. To recapitulate: A G

^{4}FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/ semiconductor field- effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G

^{4}FET can also be regarded as a single device having four gates: two side junction- based gates, a top MOS gate, and a back gate activated by biasing of a silicon- on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G

^{4}FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits implementing the same logic functions.

Optimal NOT-majority-gate, G^{4}FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G^{4}FET- and the NOR- and NAND-based designs.] In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer- programming optimization problem. The table summarizes results obtained in this study for the first four Boolean functions, showing that in most cases, fewer logic gates are needed in the NOT-majority (G^{4}FET) implementation than in the NOR- and NAND-based conventional implementations. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63 percent of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G^{4}FET-based implementations.

*This work was done by Farrokh Vatan of Caltech for NASA’s Jet Propulsion Laboratory. *

*In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to: Innovative Technology Assets Management JPL Mail Stop 202-233 4800 Oak Grove Drive Pasadena, CA 91109-8099 E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it. Refer to NPO-44407, volume and number of this NASA Tech Briefs issue, and the page number.*

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