The split-gate architecture for logic circuitry is demonstrated via a two-input logic AND circuit. To create the device, a 10-Megohm load resistor is connected between the ground and the transistor source terminals, with the two gate terminals serving as the inputs. The output (VR) is taken at the source terminal across the load resistor. A low frequency ( 0.01 Hz) square-wave signal serves as the input gate bias. For all combinations of VGS1 and VGS2, except VGS1 = VGS2 = –10 V, the transistor is in the resistive “OFF” state, and –0.3 mV < VR < 0 V. For VGS1= VGS2 – 10 V, the transistor is in the more conductive “ON” state, causing a greater portion of the voltage drop to occur across the load resistor. As a result, VR is a more negative value (–1.8 mV< VR < –1.7 mV).
When the device functions as an AND logic circuit, VGS1 and VGS2 are functions of time, while corresponding change in the output of voltage VR is a function of time for the four possible combinations of VGS1 and VGS2 = 0 or –10 V. Larger outputs are observed only when both gates are simultaneously biased “high.”
This work was done by N. Theofylaktos and F.A. Miranda of Glenn Research Center; N.J. Pinto and R. Perez of the University of Puerto Rico-Humacao; and C.H. Mueller of Analex Corporation.
Inquiries concerning rights for the commercial use of this invention should be addressed to NASA Glenn Research Center, Innovative Partnerships Office, Attn: Steve Fedor, Mail Stop 4–8, 21000 Brookpark Road, Cleveland, Ohio 44135. Refer to LEW-18214-1.