2008

Radiation-Insensitive Inverse Majority Gates

These gates would be implemented as microscopic vacuum electronic devices.

To help satisfy a need for high-density logic circuits insensitive to radiation, it has been proposed to realize inverse majority gates as microscopic vacuum electronic devices. In comparison with solid-state electronic devices ordinarily used in logic circuits, vacuum electronic devices are inherently much less adversely affected by radiation and extreme temperatures.

The proposed development would involve state-of-the-art micromachining and recent advances in the fabrication of carbon-nanotube-based field emitters. A representative three-input inverse majority gate (see figure) would be a monolithic, integrated structure that would include three gate electrodes, six bundles of carbon nanotubes (serving as electron emitters) at suitable positions between the gate electrodes, and an overhanging anode. The bundles of carbon nanotubes would be grown on degenerately doped silicon substrates that would be parts of the monolithic structure. The gate electrodes would be fabricated as parts of the monolithic structure by means of a double-silicon-on-insulator process developed at NASA’s Jet Propulsion Laboratory. The tops of the bundles of carbon nanotubes would lie below the plane of the tops of the gate electrodes. The particular choice of shapes, dimensions, and relative positions of the electrodes and bundles of carbon nanotubes would provide for both field emission of electrons from the bundles of carbon nanotubes and control of the electron current to obtain the inverse majority function, as described next.

Image
A Three-Input Inverse Majority Gate as proposed would be a microscopic vacuum electronic device containing bundles of carbon nanotubes positioned between gate electrodes to obtain controlled field emission of electrons from the bundles. In the presence of a fixed positive bias potential on the anode, the application of suitable (possibly smaller) bias potential to any two or all three gate electrodes would divert all the electron current from the anode.
The application of a positive bias potential to the anode would cause emission of electrons from the bundles of carbon nanotubes and, if no bias potential were applied to the gate electrodes, the electrons would travel to the anode, giving rise to an anode current. Relative to the anode, the gate electrodes would be much closer to the bundles of carbon nanotubes, such that the application of a smaller positive bias potential to a gate electrode would suffice to divert, to that electrode, the electrons emitted by the adjacent bundles of carbon nanotubes.

If the positive bias potential were not applied to another gate electrode, then the anode would continue to draw an electron current from the bundles of carbon nanotubes not adjacent to the positively biased gate electrode. However, if the positive bias potential were applied to any two or all three of the gate electrodes, then all of the electrons emitted by all the bundles of carbon nanotubes would be diverted to the positively biased gate electrodes, causing the anode current to fall to zero. In terms of binary logic, if one regards nonzero anode current as representing output state 1, zero anode current as representing output state 0, positive gate-electrode bias as representing input state 1, and zero gate-electrode bias as representing input state 0, then logical 0 inputs to two or all three of gate terminals would result in output of logical 1, and logical 1 inputs to two or all three of the gate terminals would result in output of logical 0. This relationship among input and output states constitutes a NAND and a NOR gate combination. This is the inverse majority function.

This work was done by Harish Manohara and Mohammad Mojarradi of Caltech for NASA’s Jet Propulsion Laboratory.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:

Innovative Technology Assets Management
JPL
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
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Refer to NPO-45388 volume and number of this NASA Tech Briefs issue, and the page number.

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