Vertical Isolation for Photodiodes in CMOS Imagers
- Created: Saturday, 01 November 2008
Diffusion cross-talk would be reduced substantially.
In a proposed improvement in complementary metal oxide/semi con ductor (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/ semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.
The left side of the figure presents a schematic cross section of a typical conventional CMOS imager pixel containing a junction diode connected to the source of a reset MOSFET. The junction diode is formed between the n well and the p epitaxial layer (or p substrate). The n well is connected to the source of the reset MOSFET through an n+ implant. The reset MOSFET and an associate source-follower MOSFET are n-type and are placed inside a p well. For reasons too complex to present in this article, the depletion width is too small to prevent lateral diffusion of photo-induced charge carriers in the undepleted (field-free) epitaxial region. In the absence of a guiding electric field, photoelectrons generated in the epitaxial layer substrate diffuse omnidirectionally between pixels, thereby causing cross-talk.
The maximum supply potential in a CMOS process is between 3 and 5 V. When potential drops are taken into account, the reverse bias across the diode is between 2 and 3 V. At these reverse biases, the p-n junction depletion width is too small to prevent diffusion cross-talk, especially for longer wavelength light, In principle, the depletion width could be increased significantly by applying a large reverse bias (e.g., 50 V) to the p epitaxial layer or substrate. However, because of (1) the electrical connection between the p well and the p epitaxial layer or substrate and (2) a requirement to keep at the most between 3 and 5 V across the CMOS devices, it is not possible to apply such a large reverse bias in this device structure. This prompts the proposed improvement in device structure.
A CMOS imager pixel as proposed, depicted on the right side of the figure, would include a deep n well and a deep p well in addition to the conventional n and p wells. The photodiode would be formed by the deep n well and the p epitaxial layer or substrate. The anode end (n end) of the diode would be connected to the n+ source implant of the reset MOSFET through the conventional n well. The reset and source-follower MOSFETs would reside in the p well as in the conventional device structure.
Unlike in the conventional device structure, the deep n well would electrostatically separate the p well in the vertical direction from the p epitaxial layer or substrate. The horizontal isolation of photodiodes in adjacent pixels from each other would be achieved by the deep p wells: Each deep p well would establish a potential barrier that would prevent electrons in the deep n wells of adjacent pixels from communicating with each other.
Inasmuch as the conventional and deep p wells would both be electrostatically isolated from the p epitaxial layer or substrate by the deep n well, any reverse (negative) bias could be applied to the p epitaxial layer or substrate without causing the potential difference between the n and p wells to increase beyond the typical conventional range of 2 to 3 V. Depending upon the resistivity of the substrate, a back-side reverse bias in excess of 50 V could be applied to achieve depletion widths as large as 50 μm, while the MOSFETs could be operated with conventional CMOS power supplies and biases. Thus, the incorporation of the deep n well and p well would allow the integration of a photodiode with a very large back-bias and very large depletion width alongside state-of-the-art MOSFETs with small supply voltages, resulting in the development of high-performance CMOS imager sensors.
This work was done by Bedabrata Pain of Caltech for NASA’s Jet Propulsion Laboratory.
In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:
Innovative Technology Assets Management
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
Refer to NPO-41226, volume and number of this NASA Tech Briefs issue, and the page number.