2008

Implementing a Digital Phasemeter in an FPGA

Firmware for implementing a digital phasemeter within a field-programmable gate array (FPGA) has been devised. In the original application of this firmware, the phase that one seeks to measure is the difference between the phases of two nominally- equal-frequency heterodyne signals generated by two interferometers. In that application, zero-crossing detectors convert the heterodyne signals to trains of rectangular pulses (see figure), the two pulse trains are fed to a fringe counter (the major part of the phasemeter) controlled by a clock signal having a frequency greater than the heterodyne frequency, and the fringe counter computes a time-averaged estimate of the difference between the phases of the two pulse trains.

Image
The Firmware Code converts two inputs (reference and measure) into a time-averaged estimate of thephase difference between the two signals.
The firmware also does the following:

•Causes the FPGA to compute the frequencies of the input signals;

•Causes the FPGA to implement an Ethernet (or equivalent) transmitter for readout of phase and frequency values; and

•Provides data for use in diagnosis of communication failures.

The readout rate can be set, by programming, to a value between 250 Hz and 1 kHz. Network addresses can be programmed by the user.

This program was written by Shanti R. Rao of Caltech for NASA’s Jet Propulsion Laboratory.

The software used in this innovation is available for commercial licensing. Please contact Karina Edmonds of the California Institute of Technology at (626) 395-2322. Refer to NPO-45575.

This Brief includes a Technical Support Package (TSP).

Implementing a Digital Phasemeter in an FPGA (reference NPO-45575) is currently available for download from the TSP library.

Please Login at the top of the page to download.

 

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