Metal plugs provide both electrical contact and alignment.
A design modification and a fabrication process that implements the modification have been conceived to solve two problems encountered in the development of back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) image-detector integrated circuits. With respect to such an integrated circuit to be fabricated on a silicon substrate, the two problems are (1) how to form metal electrical-contact pads on the back side that are electrically connected through the thickness in proper alignment with electrical contact points on the front side and (2) how to provide alignment keys on the back side to ensure proper registration of backside optical components (e.g., microlenses and/or color filters) with the frontside pixel pattern. (In this special context, “front side” signifies that face of the substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are formed.)
The fabrication process for implementing this design modification would be complex and would be subject to variation as needed for different image-detector applications. Immediately before the beginning of this process, the integrated circuitry would already have been fabricated on the front side of the substrate, as shown in the upper part of the figure. In terms that are necessarily oversimplified for the sake of brevity, the process can be summarized as follows: Through multiple steps of patterning, etching, and deposition, holes through the substrate would be formed at the desired frontside locations and the metal plugs and their protrusions would be formed in the holes. In subsequent steps, the back-side metal pads would be deposited on the metal plug protrusions, then color filters and/or microlenses would be formed between and in alignment with the metal contact pads, yielding the device structure shown in the lower part of the figure. (Not shown in the figure is a back-side antireflection coat that would be added near the end of the process.)
This work was done by Bedabrata Pain of Caltech for NASA’s Jet Propulsion Laboratory.
In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:
Innovative Technology Assets Management
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
Refer to NPO-42839, volume and number of this NASA Tech Briefs issue, and the page number.
This Brief includes a Technical Support Package (TSP).
Making a Back-Illuminated Imager With Back-Side Contact and Alignment Markers (reference NPO-42839) is currently available for download from the TSP library.
Please Login at the top of the page to download.