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Economical Implementation of a Filter Engine in an FPGA
 Created: Thursday, 01 January 2009
There are numerous potential uses in general signal processing.
A logic design has been conceived for a fieldprogrammable gate array (FPGA) that would implement a complex system of multiple digital statespace filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources.
A digital statespace filter of the type to which the design applies (see figure) is represented by the equations
x(k + 1) = Ax(k) + Bu(k) (1)
and
y(k) = Cx(k) + Du(k) (2)
where:
The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register.
A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a “valid” signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations.
This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be advantageous to combine compact FPGA digital filter implementations with other applicationspecific logic implementations on single integratedcircuit chips. An FPGA could readily be tailored to implement a variety of filters because the filter coefficients would be loaded into memory at startup.
This work was done by James E. Kowalski
of Caltech for NASA’s Jet Propulsion
Laboratory.
NPO44662.
This Brief includes a Technical Support Package (TSP).
Economical Implementation of a Filter Engine in an FPGA (reference NPO44662) is currently available for download from the TSP library.
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