FPGA Boot Loader and Scrubber
- Friday, 04 September 2009
A computer program loads configuration code into a Xilinx field-programmable gate array (FPGA), reads back and verifies that code, reloads the code if an error is detected, and monitors the performance of the FPGA for errors in the presence of radiation. The program consists mainly of a set of VHDL files (wherein “VHDL” signifies “VHSIC Hardware Description Language” and “VHSIC” signifies “very-high-speed integrated circuit”).
The first of three parts of the program loads the configuration code from a flash memory device by means of an industry-standard interface. The second part continuously reads back the configuration data stream through the interface, calculates a cyclic redundancy code (CRC) on the data, and compares the calculated CRC values with values stored in the flash memory device. If the calculated CRC values do not match the stored values, the configuration data memory is cleared and the configuration data are reloaded. The third part of the program implements a watchdog register, to which the FPGA is required to write at regular intervals. If the FPGA fails to write to the register within a required time, the configuration memory is cleared and the configuration data are reloaded.
This program was written by Randall S. Wade of Johnson Space Center and Bailey Jones of Jacobs Sverdrup. MSC-24124-1
This Brief includes a Technical Support Package (TSP).
FPGA Boot Loader and Scrubber (reference MSC-24124-1) is currently available for download from the TSP library.
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