High-voltage input circuitry would be combined with standard low-voltage CMOS circuitry.
A proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, “low” and “high” refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure.
Several Performance Parameters of the proposed level translator were extracted from results of com- putational simulations. The proposed circuit schematic is shown." class="caption" align="right">Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need.
In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output.
The common-mode-sensing pair would be used to set the control potential for a biasing circuit that would provide the proper terminal potentials for protecting all devices against excessive excursions of potential for a common-mode potential range of 0 to 12 V. The biasing circuit would include high-voltage-drain transistors capable of withstanding the full high input potentials on their drains; the incorporation of these transistors would enable simplification of part of the bias circuit and of the circuitry associated with the input transistor pairs. High-voltage n-wells would enable floating of substrates of pchannel metal oxide/semiconductor field-effect transistors to potentials as high as tens of volts, whereas devices containing standard n-wells break down at potentials between 6 and 7 V, even though maximum gate-to-source and drain-to-source potentials remain at 3.3 V.
The expected performance of the circuit has been studied in computational simulations. The table presents values of some performance parameters determined from the results of the simulations.
This work was done by Jeremy A. Yager, Mohammad M. Mojarradi, and Tuan A. Vo of Caltech and Benjamin J. Blalock from University of Tenn., Knoxville for NASA’s Jet Propulsion Laboratory. NPO-45762
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