MathWorks (Natick, MA) has announced HDL Coder, which automatically generates
HDL code from MATLAB, allowing engineers to implement FPGA and ASIC designs
from the widely used MATLAB language. MathWorks also announced HDL Verifier,
which includes FPGA hardware-in-the-loop capabilities for testing FPGA and
ASIC designs. With these two products, MathWorks now provides HDL code
generation and verification across MATLAB and Simulink. HDL Coder generates
portable, synthesizable VHDL and Verilog code from MATLAB functions and
Simulink models that can be used for FPGA programming or ASIC prototyping and
design. As a result, engineering teams can now immediately identify the best
algorithm for hardware implementation. Traceability between Simulink models
and generated HDL code also supports the development of high-integrity
applications that adhere to DO-254 and other standards.
This week's Question: Fox Sports offered virtual-reality streams from last week's U.S. Open, a major golf championship in Oakmont, PA. Sports fans who owned the right devices could watch the golf event on the television while using VR for...
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