Sample-Clock Phase-Control Feedback
- Created on Friday, 01 June 2012
The throughput of a pulse-position modulation with 16 slots can increase from 188 Mb/s to 1.5 Gb/s.
To demodulate a communication signal, a receiver must recover and synchronize to the symbol timing of a received waveform. In a system that utilizes digital sampling, the fidelity of synchronization is limited by the time between the symbol boundary and closest sample time location. To reduce this error, one typically uses a sample clock in excess of the symbol rate in order to provide multiple samples per symbol, thereby lowering the error limit to a fraction of a symbol time. For systems with a large modulation bandwidth, the required sample clock rate is prohibitive due to current technological barriers and processing complexity. With precise control of the phase of the sample clock, one can sample the received signal at times arbitrarily close to the symbol boundary, thus obviating the need, from a synchronization perspective, for multiple samples per symbol.Sample-clock phase-control feedback was developed for use in the demodulation of an optical communication signal, where multi-GHz modulation bandwidths would require prohibitively large sample clock frequencies for rates in excess of the symbol rate. A custom mixed-signal (RF/digital) offset phase-locked loop circuit was developed to control the phase of the 6.4-GHz clock that samples the photoncounting detector output. The offset phase-locked loop is driven by a feedback mechanism that continuously corrects for variation in the symbol time due to motion between the transmitter and receiver as well as oscillator instability. This innovation will allow significant improvements in receiver throughput; for example, the throughput of a pulse-position modulation (PPM) with 16 slots can increase from 188 Mb/s to 1.5 Gb/s.
The novelty of this innovation is precise control of the sample-clock phase supports synchronization to the symbol timing of the received waveform without the use of a sample clock in excess of the symbol rate. This can reduce the required sample clock frequency for demodulation of a communication signal, and thereby reduce the processing complexity as well as permit demodulation of large bandwidth signals for which there was a technological barrier to a sample frequency in excess of the symbol rate.
Sample-clock phase-control feedback has direct applications in optical and radio frequency communication systems for satellite and deep space applications, as well as other applications in high-precision timing.
This work was done by Kevin J. Quirk, Jonathan W. Gin, Danh H. Nguyen, and Huy Nguyen of Caltech for NASA’s Jet Propulsion Laboratory. NPO-47663
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