Measurement Techniques for Clock Jitter
- Created on Saturday, 01 September 2012
New approach offers more advanced coded modulation techniques.
NASA is in the process of modernizing its communications infrastructure to accompany the development of a Crew Exploration Vehicle (CEV) to replace the shuttle. With this effort comes the opportunity to infuse more advanced coded modulation techniques, including low-density parity-check (LDPC) codes that offer greater coding gains than the current capability. However, in order to take full advantage of these codes, the ground segment receiver synchronization loops must be able to operate at a lower signal-to-noise ratio (SNR) than supported by equipment currently in use.At low SNR, the receiver symbol synchronization loop will be increasingly sensitive to transmitter timing jitter. Excessive timing jitter can cause bit slips in the receiver synchronization loop, which will in turn cause frame losses and potentially lead to receiver and/or decoder loss-of-lock. Therefore, it is necessary to investigate what symbol timing jitter requirements on the satellite transmitter are needed to support the next generation of NASA coded modulation techniques.
Measurements of ground segment receiver sensitivity to transmitter bit jitter were conducted using a satellite transponder and two different commercial staggered quadrature phase-shift keying (SQPSK) receivers. The symbol synchronizer loop transfer functions were characterized for each receiver. Symbol timing jitter was introduced at the transmitter. Effects of sinusoidal (tone) jitter on symbol error rate (SER) degradation and symbol slip probability were measured. These measurements were used to define regions of sensitivity to phase, frequency, and cycle-to-cycle jitter characterizations. An assortment of other band-limited jitter waveforms was then applied within each region to identify peak or root-mean-square measures as a basis for comparability.
Receiver clock recovery loops that operate in low SNR ratio environments require that transmit clock jitter be constrained by several measures on different dimensions and operating regions. In this work, effects of transmit phase jitter (PhJ), frequency jitter (FJ), and cycle-to-cycle jitter (CCJ) were studied for sinusoidal and multi-tone jitter profiles on receiver performance. It was demonstrated that the receiver must have a loop bandwidth tight enough to avoid cycle slips, but loose enough to track some movement in the data signal. Movement that a tight loop cannot track is usually manifested first as intersymbol interference (ISI) (SER degradation) and then ultimately as cycle slipping in the receiver.
Results from the tests indicate that the receiver symbol synchronization loop is more sensitive to certain types of symbol jitter and jitter frequencies, depending on the selection of the loop filter and damping ratio. A framework is provided to properly compose a transmit jitter mask depending on receiver design parameters such as damping ratio in order to limit receiver performance degradation at low SNR regions.
This work was done by Chatwin Lansdowne and Adam Schlesinger of Johnson Space Center. MSC-24810-1
This Brief includes a Technical Support Package (TSP).
Measurement Techniques for Clock Jitter (reference MSC-24810-1) is currently available for download from the TSP library.
Please Login at the top of the page to download.