NASA’s Jet Propulsion Laboratory, Pasadena, California
New applications such as high-data-rate, photon-starved, free-space optical communications require photon counting at flux rates into gigaphoton-per-second regimes coupled with sub-nanosecond timing accuracy. Current single-photon detectors that are capable of handling such operating conditions are designed in an array format and produce output pulses that span multiple sample times. In order to discern one pulse from another and not to over-count the number of incoming photons, a detection algorithm must be applied to the sampled detector output pulses. As flux rates increase, the ability to implement such a detection algorithm becomes difficult within a digital processor that may reside within a field-programmable gate array (FPGA).