As NASA embarks upon deep-space human exploration, the next-generation extravehicular activity (EVA) radio will be a pivotal technology and an integral part of lunar surface systems success. It facilitates surface operations, enables crew mobility, and supports point to multi-point communications across rovers, landers, habitat, and other astronauts. Driven by Com - m unications, Command, Control, and Information (C3I) interoperability, stringent power budgets, and miniaturization, this mobile radio platform has become increasingly complex. To achieve the overarching communication goals of small form factor, ultrapower, and reconfigurability, NASA needs to advance power-aware processing technology.
With a scant EVA radio power budget of less than four watts, the S-band (2.4- 2.483 Ghz) adaptive radio must deliver voice, telemetry, and high-definition motion imagery transmissions. It’s not enough to optimize power at design time, but dynamic power management must be employed to ensure power efficiency.
For the EVA radio to connect highly diverse data traffic among changing network topologies demands supportability of a wide array of applications with potentially extreme operating conditions. This requires intelligent, poweraware hardware. This power-aware system denotes continuously adaptive circuits, architectures, algorithms, and protocols that sense the instantaneous performance requirements and environment constraints (including available power sources) to dynamically optimize total energy. The resulting power savings can easily exceed an order of magnitude. This model relies on ultra-low-energy digital circuits to enable “cognitive” sensing of the instantaneous requirements/ constraints and perform sophisticated signal-processing in specific response. For instance, local data-processing and advanced signal representation, requiring rich encoding/decoding, can drastically reduce radio data payload (especially necessary during poor channel conditions), and adaptive error-correction algorithms can maintain reliability even as environment/energy constraints worsen. Hence, system components must dynamically adapt, over a performance range of hundreds of mega-Hertz to sub kilo-Hertz, while operating, in coordination with one another to minimize total energy.
NASA seeks power-aware technology advancement in the following areas:
- Variation-tolerant, performance-scalable architectures: Hardware must sense its own limitation at a dynamically varying, performance-driven optimal energy operating point, and reconfigure accordingly. If variability is stressed at the low-voltage operating point, redundant hardware should be used to improve reliability; if throughput is stressed at the high-performance operating point, redundant hardware should be used to increase parallelism.
- Highly agile platform components (SRAM and logic): Circuits should use functionality assists, including selective biasing, leakage-control, routing resources, etc., that get engaged dynamically depending on the operating point.
- Energy-aware algorithms for adaptive hardware: Algorithms must be aware of the different hardware operating points and associated architecture. For instance, during low-power modes targeting voice and data (for telemetry), occasional high-throughput app lications (like high-motion imagery) should dynamically switch to algorithms employing extreme parallelism in order to support a minimum operating voltage.
- Extreme power converters: In order to minimize off-chip components, DCDC converters should use a single reconfigurable architecture that efficiently delivers load powers ranging from micro-Watts at low voltages, to Watts at high voltages.