Using RapidIO® Technology as a System-Level Fabric
- Created on Saturday, 01 September 2007
One potential point of confusion is the fact that the Serial RapidIO electrical layer is effectively a XAUI interface. Many developers associate XAUI with Ethernet and mistakenly assume that all XAUI backplanes are Ethernet based. Serial RapidIO was intentionally designed to match the XAUI specification so that developers using Serial RapidIO could leverage the existing XAUI ecosystem that Ethernet has already developed. This is another key strength of Serial RapidIO as its 3 data rates all follow standard specifications: 1.25 Gbps follows 1000 Base-X, 2.5 Gbps follows PCI-Express, and 3.125 Gbps follows XAUI. By basing the electrical layer on these three very mature eco-systems, Serial RapidIO has been able to take advantage of interface economies of scale from its inception.
Serial RapidIO was designed from the start to minimize overhead and latency for chip-to-chip data transfers. Certainly, one can force any interconnect into any application, but the results will be less than optimal, and this is a fact that developers who select Ethernet for backplane, inter-chassis, and other system-level fabric applications because they are familiar with it quickly discover. Currently there is an Ethernet backplane standard under development which is attempting to address the inefficiencies of Ethernet for chip-to-chip interconnections, but it is not yet available. However, even if its inefficiencies have been sufficiently addressed once it is finalized, it will lack the extensive ecosystem and widespread industry support that Serial RapidIO already enjoys today.