Quad First Stage Processor: A Four-Channel Digitizer and Digital Beam-Forming Processor
- Saturday, 01 March 2014
- NASA’s Jet Propulsion Laboratory, Pasadena, California
A 4-channel digitizer was designed, built, and tested. The very large, complex board enables SweepSAR. The proposed Deformation, Eco-Systems, and Dynamics of Ice Radar (DESDynl-R) Lband SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with very fine synchronization and digital beam forming are necessary in order to facilitate this new technique.
The Quad First Stage Processor (qFSP) was developed to achieve both the processing performance as well as the digitizing fidelity in order to accomplish this sweeping SAR technique. The qFSP utilizes high-precision and highspeed analog-to-digital converters (ADCs), each with a finely adjustable clock distribution network to digitize the channels at the fidelity necessary to allow for digital beam forming. The Xilinx-produced FX130T Virtex 5 part handles the processing to digitally calibrate each channel as well as filter and beam-form the receive signals.
Demonstrating the digital processing required for digital beam forming and digital calibration is instrumental to the viability of the proposed DESDynl instrument. The qFSP development brings this implementation to Technology Readiness Level (TRL) 6.
This work was done by Chung-Lun Chuang, Scott J. Shaffer, Robert F. Smythe, Eric N. Liao, Samuel S. Li, Arin C. Morfopoulos, Louise A. Veilleux, Chester N. Lim, and Noppasin Niamsuwan of Caltech for NASA’s Jet Propulsion Laboratory. NPO-48936