This processor is a reconfigurable FPGA-based electronics payload for advanced data processing applications.
The COVE (CubeSat Onboard processing Validation Experiment) Payload Processor is JPL’s first on-orbit demonstration with the Xilinx Virtex-5 FPGA (field-programmable gate array). The electronics payload is designed to provide a platform for advanced data processing applications while conforming to CubeSat specifications. Measuring 9 × 9.5 × 2 cm, COVE carries the new radiation-hardened Virtex-5 FPGA (V5QV), magnetoresistive RAM (MRAM), and phase-change memory. All data access to/from the payload is facilitated through a shared memory interface via a direct serial peripheral interface (SPI). Multiple configuration options enable COVE to be reconfigured in flight with new FPGA firmware.
Part of the M-Cubed CubeSat (University of Michigan), COVE is designed to demonstrate a data processing algorithm for the Multiangle SpectroPolarimetric Imager (MSPI) instrument currently under development at JPL. COVE executes the data processing algorithm on image data provided to it by M-Cubed from its CMOS camera. The raw image data is sent directly to shared memory on the COVE payload, and, when requested, the processing results are read back from the same memory.
The COVE payload is designed with multiple power modes that enable the payload to save significant power when not actively processing data. Raw image data and processed results are written to and read back from COVE in a low power mode, where only the interfaces and shared memory are enabled and the FPGA remains off. Only during data processing is power provided to the FPGA.
The COVE payload processor has multiple ADCs to record housekeeping data. When the FPGA is on, all secondary board voltages, currents, and FPGA temperature are sampled by the ADCs and logged to shared memory. The MCubed flight computer downloads this data together with the image processing results prior to performing a transmission to ground stations.
The FPGA can be configured from multiple sources. A Xilinx XQF32P PROM is programmed on the ground and holds the “golden” configuration bitstream (FPGA firmware) for the experiment. This configuration cannot be overwritten in flight. A secondary FPGA configuration is stored in the shared memory and can be rewritten in flight. A discreet I/O line, controlled from the flight computer, tells the FPGA which configuration to boot on power-up. This dual-configuration design enables the COVE payload to be re-purposed for future experiments once the primary mission is completed.
M-Cubed was launched on October 28, 2011, from Vandenberg Air Force Base (VAFB) as a secondary payload of the NPP Mission. A post P-Pod deployment anomaly resulted in the inability to command M-Cubed, and therefore the COVE payload was not demonstrated on orbit. COVE-2 and a re-flight of M-Cubed was funded by NASA’s Earth Science Technology Office in May 2012 and was launched on December 5, 2013.
This work was done by Paula J. Pingree, Dmitriy L. Bekker, Brian R. Franklin, Andrew T. Klesh, Nooshin Meshkaty, Chris S. Peay, Thomas A. Werne, and Thor O. Wilson of Caltech; and Alireza Bakhshi of BA Engineering for NASA’s Jet Propulsion Laboratory. NPO-48112
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COVE: A CubeSat Payload Processor (reference NPO-48112) is currently available for download from the TSP library.
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