Electronic circuits that operate in high temperatures are used in automobiles, airplanes, oil drilling operations, and many other applications.

The use of patterned multiple layers of thin films of metal and dielectric to form integrated circuit interconnections of transistors and/or form on-chip circuit capacitors is well known to those skilled in the art of semiconductor microelectronic fabrication. Because differing layers of thin film materials have different physical and thermal expansion properties, it is also well known that stress is inherently present in these multilayer film structures on a microelectronic chip. The amount of stress changes with temperature and as a function of lateral feature size/area across the chip. When stress anywhere within a patterned metal film feature becomes critically large (i.e., the “yield stress” is exceeded), the metal film can physically crack, buckle, or delaminate from other layers, which usually damages/fails the intended electrical operation of the microelectronic circuit.

Other factors being roughly equal, it’s more difficult to avoid stress buildup and resulting buckling/delamination damage for extreme-temperature integrated circuits that function over a much broader temperature range than conventional integrated circuits designed for conventional (room) temperature applications (like computers and cellphones). Since on-chip metal-insulator-metal capacitors typically require much larger lateral area metal features (i.e., the metal plates of the on-chip capacitor), the stress buildup problem is most acute for these devices. A “stress-managed” metal-insulator-metal capacitor structure has been recently implemented in a prototype extreme-environment integrated circuit process. The 15-picofarad prototype capacitors have been shown to successfully withstand temperatures above 700 °C. The top and bottom metallizations are tantalum silicide (TaSi2) about 0.8 micrometers thick that are sputter-deposited via a close-proximity (target to substrate distance of less than 3 cm) sputter deposition process, while the insulator layer is a 1-micrometer-thick layer of SiO2 deposited at 720 °C by low-pressure chemical vapor deposition (LPCVD) using tetraethyl orthosilicate (TEOS) precursor.

This work was done by David Spry and Philip Neudeck of Glenn Research Center. NASA is seeking partners to further develop this technology through joint cooperative research and development. For more information about this technology and to explore opportunities, please contact This email address is being protected from spambots. You need JavaScript enabled to view it.. LEW-19386-1

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