This innovation is capable of correlating two analog signals by using an analog- based signal conditioning front end to hard-limit the analog signals through adaptive thresholding into a binary bit stream, then performing the correlation using a Hamming “similarity” calculator function embedded in a one-bit digital correlator (OBDC). By converting the analog signal into a bit stream, the calculation of the correlation function is simplified, and less hardware resources are needed. This binary representation allows the hardware to move from a DSP where instructions are performed serially, into digital logic where calculations can be performed in parallel, greatly speeding up calculations.

Each of two analog signals (channels A and B) is converted to a digital bit stream by phase correcting it and comparing it to an average of itself at a sampling clock rate *f*. The hard-limited conversions of A and B are bitwise compared to measure the level of similarity between the two by the OBDC. This similarity measurement *X* is equal to the maximum possible Hamming distance (*N* bits in disagreement) minus the measured number of bits in disagreement.

The OBDC functions are embedded into a field programmable gate array (FPGA). The OBDC is made up of two shift registers containing the current sample values (of length *N*) from each of the two input channels (A and B). During each sample clock, a new sample from each A and B input is clocked into the input linear shift register for each respective channel; this input shifts the current values in the linear shift register. The oldest (*N* + 1 sample clocks ago) sample is clocked out of the register. Once the inputs have been clocked in, the correlation routine can start. This rising edge of the sample clock also clears the max correlation value, the best correlation index, and the shift counter registers, initializing the correlator.

When the two registers match exactly, or are correlated, the *X* value will equal *N*. Once the correlation value has been calculated, this result is forwarded to compare with the max correlation value register. If the *X* value is greater than the current max correlation value, then the max correlation value becomes *X*, and the shift counter register is latched and put into the best correlation index register, providing the index of the current best correlation.

This index is the number of sample clock periods difference between the two input signals and thus, for sample clock rate *f*, indicates the delay between the signals A and B.

*This work was done by Norman Prokop and Michael Krasowski of Glenn Research Center. *

* Inquiries concerning rights for the commercial use of this invention should be addressed to NASA Glenn Research Center, Innovative Partnerships Office, Attn: Steven Fedor, Mail Stop 4–8, 21000 Brookpark Road, Cleveland, Ohio 44135. LEW-18902-1*

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