The Multithreaded Microbenchmarks for Processor-InMemory (PIM) Compilers, Simulators, and Hardware are computer programs arranged in a series for use in testing the performances of PIM computing systems, including compilers, simulators, and hardware. The programs at the beginning of the series test basic functionality; the programs at subsequent positions in the series test increasingly complex functionality. The programs are intended to be used while designing a PIM system, and can be used to verify that compilers, simulators, and hardware work correctly. The programs can also be used to enable designers of these system components to examine tradeoffs in implementation. Finally, these programs can be run on non-PIM hardware (either singlethreaded or multithreaded) using the POSIX pthreads standard to verify that the benchmarks themselves operate correctly. (POSIX -Portable Operating System Interface for UNIX- is a set of standards that define how programs and operating systems interact with each other. pthreads is a library of pre-emptive thread routines that comply with one of the POSIX standards).
These programs were written by Daniel S. Katz of Caltech for NASA’s Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Semiconductors & ICs category.
This software is available for commercial licensing. Please contact Karina Edmonds of the California Institute of Technology at (818) 393-2827. Refer to NPO-41206.
This Brief includes a Technical Support Package (TSP).
Programs for Testing Processor-in-Memory Computing Systems (reference NPO-41206) is currently available for download from the TSP library.
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