Improved On-Chip Measurement of Delay in an FPGA or ASIC
- Created on Friday, 01 June 2007
Input and output buffers and the associated delays are eliminated.
An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). Heretofore, it has been the usual practice to use either of two other types of on-chip delay-measuring circuits:
- A delay chain of inverters is incorporated into the FPGA or ASIC chip along with an input port for feeding the inverter chain and an output port for feeding a signal to off-chip measurement circuitry. The disadvantage of this design is that the measurement is inaccurate because it includes delays in buffers that are parts of the input and output ports.
- The delay chain is arranged as a ring oscillator. The disadvantage of this design is that the delay chain does not always oscillate as expected.
The improved design overcomes the disadvantages of both older designs. In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.
Also on the external board are two crystal-controlled oscillators. One oscillator generates a clock signal at a nominal frequency of 50 MHz; the other generates a clock signal, at a nominal frequency of 33 MHz, which is not synchronized with the 50-MHz signal. The 50- MHz signal is used for the majority of the FPGA logic. The 33-MHz signal is fed to an on-chip pulse-duration-measuring unit.