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Improved On-Chip Measurement of Delay in an FPGA or ASIC

The on-chip delay-measuring circuitry includes a pulse-generator unit, wherein the 50-MHz signal is divided in frequency to generate two outputs: (1) a 1- pulse-per-second clock signal that is fed to the on-chip pulse-duration- measuring unit and (2) a train of pulses, at frequency of 125 kHz, that is fed as input to the delay chain.

A gate that follows the multiplexer accepts inputs from both ends of the delay chain. In response, the gate generates a 125-kHz train of pulses, the duration of which equals the delay. This pulse train is fed to the pulse-durationmeasuring unit. The duration of the pulses in this train is what is measured. The complexity of the pulse-durationmeasurement process is such that a complete description is not possible within the space available for this article. It must suffice to summarize by saying that the process involves a combination of sampling the 125-kHz pulses by use of the 33-MHz clock signals during a fixed period of 1 second, counting the numbers of sampling periods during which the pulses are on, then averaging and displaying the result.

This work was done by Yuan Chen, Gary Burke, and Douglas Sheldon of Caltech for NASA’s Jet Propulsion Laboratory. For more information, download the Technical Support Package (free white paper) at www.techbriefs. com/tsp under the Semiconductors & ICs category.

This invention is owned by NASA, and a patent application has been filed. Inquiries concerning nonexclusive or exclusive license for its commercial development should be addressed to the Patent Counsel, NASA Management Office–JPL. Refer to NPO-43348.

This Brief includes a Technical Support Package (TSP).

Improved On-Chip Measurement of Delay in an FPGA or ASIC (reference NPO-43348) is currently available for download from the TSP library.

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