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Cumulative Timers for Microprocessors

The internal implementation would function similarly to the external implementation, except that the serial number and the prescaler-reduced count of clock cycles would be stored in either (1) part of the flash RAM used by the rest of the microprocessor or (2) a separate flash RAM dedicated to the timer. It would be necessary to design the microprocessor hardware and software so that there would be no way to decrement the count or otherwise exert external control over the timer flash RAM.

This work was done by John O. Battle of Caltech for NASA’s Jet Propulsion Laboratory. For more information, download the Technical Support Package (free white paper) at www.techbriefs.com/tsp under the Semiconductors & ICs category. In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to: Innovative Technology Assets Management JPL Mail Stop 202-233 4800 Oak Grove Drive Pasadena, CA 91109-8099 (818) E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it. Refer to NPO-43599, volume and number of this NASA Tech Briefs issue, and the page number.

This Brief includes a Technical Support Package (TSP).

Cumulative Timers for Microprocessors (reference NPO-43599) is currently available for download from the TSP library.

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