Two developments improve the utilization of flash memory devices in the face of the following limitations: (1) a flash write element (page) differs in size from a flash erase element (block), (2) a block must be erased before its is rewritten, (3) lifetime of a flash memory is typically limited to about 1,000,000 erases, (4) as many as 2 percent of the blocks of a given device may fail before the expected end of its life, and (5) to ensure reliability of reading and writing, power must not be interrupted during minimum specified reading and writing times.

The first development comprises interrelated software components that regulate reading, writing, and erasure operations to minimize migration of data and unevenness in wear; perform erasures during idle times; quickly make erased blocks available for writing; detect and report failed blocks; maintain the overall state of a flash memory to satisfy real-time performance requirements; and detect and initialize a new flash memory device.

The second development is a combination of hardware and software that senses the failure of a main power supply and draws power from a capacitive storage circuit designed to hold enough energy to sustain operation until reading or writing is completed.

This work was done by Thomas K. Gender, James Chow, and William E. Ott of Honeywell, Inc., for Johnson Space Center. For further information, contact the Johnson Commercial Technology Office at (281) 483-3809.

Title to this invention has been waived under the provisions of the National Aeronautics and Space Act {42 U.S.C. 2457(f)}, to Honeywell. Inquiries concerning licenses for its commercial development should be addressed to:

Satellite Systems Operation

Honeywell, Inc.

19019 N. 59th Avenue

Glendale, AZ 85308

Phone: (602) 313-5000

Refer to MSC-23465-1/6-1, volume and number of this NASA Tech Briefs issue, and the page number.

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