Tech Briefs

Digital Synchronizer Without Metastability

A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop.

The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals — one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.

This work was done by Robert M. Simle and Jose A. Cavazos of Lockheed Martin Corp. for Johnson Space Center.

Title to this invention, covered by U.S. Patent No. 6,771,099 B2, has been waived under the provisions of the National Aeronautics and Space Act {42 U.S.C. 2457 (f)}. Inquiries concerning licenses for its commercial development should be addressed to:

Lockheed Martin General Counsel
Lockheed Martin
2400 NASA Road 1
Houston, TX 77258

Refer to MSC-23220-1, volume and number of this NASA Tech Briefs issue, and the page number.