Reconfigurable, Bi-Directional Flexfet Level Shifter for Low- Power, Rad-Hard Integration
- Created on Tuesday, 01 December 2009
These level shifters enable the development of multi-level voltage systems.Two prototype Reconfigurable, Bidirectional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex - fet Inde pend ently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) doublegated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes.
The primary technical objectives were
to develop a high-voltage, thick oxide
option for the 180-nm Flexfet process,
and to develop a stand-alone ReBiLS IC
with two 8-channel I/O busses, 1.8–2.5
I/O on the low-voltage pins, 5.0-V-tolerant
input and 3.3-V output I/O on the
high-voltage pins, and 100-MHz minimum
operation with 10-pF external
Another objective was to develop an
embedded, rad-hard ReBiLS I/O cell
with 0.5-V low-voltage operation for
interface with core logic, 5.0-V-tolerant
input and 3.3-V output I/O pins, and
100-MHz minimum operation with 10-
pF external loads.
A third objective was to develop a 0.5-
V Reed-Solomon Encoder with embedded
- Transfer the existing CULPRiT RS encoder from a 0.35-μm bulk-CMOS process to the ASI 180-nm Flexfet, radhard SOI Process.
- 0.5-V low-voltage core logic.
- 5.0-V-tolerant input and 3.3-V output I/O pins.
- 100-MHz minimum operation with 10- pF external loads.
The stand-alone ReBiLS chip will
allow system designers to provide efficient
between components operating at different
voltages. Embedding the ReBiLS
cells into the proven Reed-Solomon
encoder will demonstrate the ability to
support new product development in a
commercially viable, rad-hard, scalable
180-nm SOI CMOS process.
This work was done by Kelly DeGregorio and Dale G. Wilson of American Semiconductor, Inc. for Goddard Space Flight Center. For more information, download the Technical Support Package (free white paper) at www.techbriefs.com/tsp under the Semiconductors & ICs category. GSC- 15565-1