Improved Method of Manufacturing SiC Devices
- Thursday, 04 January 2007
Several improvements promise to make manufacture of SiC devices more economical.
The phrase, “common-layered architecture for semiconductor silicon carbide” (“CLASSiC”) denotes a method of batch fabrication of microelectromechanical and semiconductor devices from bulk silicon carbide. CLASSiC is the latest in a series of related methods developed in recent years in continuing efforts to standardize SiC-fabrication processes. CLASSiC encompasses both institutional and technological innovations that can be exploited separately or in combination to make the manufacture of SiC devices more economical. Examples of such devices are piezoresistive pressure sensors, strain gauges, vibration sensors, and turbulence-intensity sensors for use in harsh environments (e.g., high-temperature, high-pressure, corrosive atmospheres).
The institutional innovation is to manufacture devices for different customers (individuals, companies,and/or other entities) simultaneously in the same batch. This innovation is based on utilization of the capability for fabrication, on the same substrate, of multiple SiC devices having different functionalities (see figure). Multiple customers can purchase shares of the area on the same substrate, each customer’s share being apportioned according to the customer’s production- volume requirement. This makes it possible for multiple customers to share costs in a common foundry, so that the capital equipment cost per customer in the inherently low-volume SiC-product market can be reduced significantly.
One of the technological innovations is a five-mask process that is based on an established set of process design rules. The rules provide for standardization of the fabrication process, yet are flexible enough to enable multiple customers to lay out masks for their portions of the SiC substrate to provide for simultaneous batch fabrication of their various devices. In a related prior method, denoted multi-user fabrication in silicon carbide (MUSiC), the fabrication process is based largely on surface micromachining of poly SiC. However, in MUSiC one cannot exploit the superior sensing, thermomechanical, and electrical properties of single-crystal 6H-SiC or 4H-SiC. As a complement to MUSiC, the CLASSiC five-mask process can be utilized to fabricate multiple devices in bulk single-crystal SiC of any polytype. The five-mask process makes fabrication less complex because it eliminates the need for large-area deposition and removal of sacrificial material.
Other innovations in CLASSiC pertain to selective etching of indium tin oxide and aluminum in connection with multilayer metallization. One major characteristic of bulk micromachined microelectromechanical devices is the presence of three-dimensional (3D) structures. Any 3D recesses that already exist at a given step in a fabrication process usually make it difficult to apply a planar coat of photoresist for metallization and other subsequent process steps. To overcome this difficulty, the CLASSiC process includes a reversal of part of the conventional flow: Metallization is performed before the recesses are etched.
The metallization is followed by the deposition and lift-off of aluminum and indium tin oxide etch masks on the entire planar SiC substrate surface except where the recesses are to be created.
After etching of the recesses, the aluminum and indium tin oxide etch masks are selectively etched to leave a stack of underlying metals (example, titanium, tantalum silicide, and platinum). Thus, the aluminum and indium tin oxide serve as protective layers for the metallization while also functioning as etch masks during deep reactive-ion etching to create the desired 3D structures. After removal of the aluminum and indium tin oxide, wires can be bonded onto the top platinum layer to provide for transition of electrical signals to/from the device.
This work was done by Robert S. Okojie of Glenn Research Center. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Semiconductors & ICs category. Inquiries concerning rights for the commercial use of this invention should be addressed to NASA Glenn Research Center, Innovative Partnerships Office, Attn: Steve Fedor, Mail Stop 4–8, 21000 Brookpark Road, Cleveland, Ohio 44135. Refer to LEW-17170.