Photonics Design Automation
- Created on Tuesday, 01 January 2013
Using Photonic Design Automation Tools
A designer of a Photonic Integrated Circuit (PIC) starts by modeling any components that are not part of a foundry's standard building blocks through the use of a propagation simulator. Once those building blocks are defined, the designer can combine them together with the foundry's standard building blocks and analyze the performance of a complete chip using a circuit simulator. It is through the use of design kits that the foundry's standard building blocks become available to the PIC designer. In the circuit simulator, the wavelength dependent scattering matrix of each building block is used to efficiently calculate the overall behavior of the chip. The designer can thus quickly optimize a photonic integrated circuit for best performance, highest yield, lowest cost, and robustness against manufacturing tolerances.
One particular advantage of working with Photonics Design Automation is that a foundry can make available unique building blocks that are covered by patents or trade secrets. The unique building block is shown as a bounding box that hides what is inside the box, but does detail the location of input and output waveguides as well as the functionality of the building block through a wavelength dependent scattering matrix.
Once a satisfactory design has been created with a specific foundry and package in mind, it can be transferred via the PDA framework to MaskEngineer or other mask layout software. The mask layout can then be further optimized, after which the PIC design is translated into mask files. During this process, automatic post processing takes place that obeys design rules set by the foundry. For example, a waveguide may have to be wider on the mask than in the original design in order to compensate for a known amount of underetch. Or the definition of a waveguide may involve a local mask inversion if the waveguide is created using lift-off rather than through etching. In addition, the PDA framework will perform foundry specific design rule checks (DRC) at the logical and mask levels. The design can, for example, be checked for the minimum allowable bending radius. Or a check is performed to ensure that metalization and waveguide layers are neither overlapping nor closer than a minimum distance.
The designer will subsequently send the mask files to the foundry, which performs final processing. If a protected building block is used, the foundry will replace the bounding box with the actual design layout. The foundry may also add process control modules. And when the PIC design is part of a Multi Project Wafer (MPW) run, the foundry will collect the mask files from all participating users and place them in individual reticles. When the mask set is ready, the wafers can then be processed by the foundry.
Multi Project Wafer Runs
While Photonic Design Automation delivers indispensable tools to streamline chip runs for foundries and creates a firsttime- right environment for PIC designers, PDA brings an additional reduction of development costs by enabling Multi Project Wafer (MPW) runs. In a Multi Project Wafer run, the costs for chip fabrication, masks and set-up time are shared between multiple users. This significantly reduces the barrier to photonic integration and allows photonic chips to be introduced for smaller volume applications than hitherto possible.
Photonics Design Automation as described in this article has been successfully applied to (MPW) runs in InP, TriPleX, as well as silicon photonics technologies. Moreover, the effective use of PDA in well over 100 designs using six different foundries and two packaging providers in less than a year demonstrates that photonics can indeed greatly benefit from leveraging these automation tools. Note that PDA is not only indispensable for photonic foundries, the same approach can be just as beneficial for an in-house wafer fab. The PDA framework also allows third parties to develop versatile libraries of building blocks or to introduce convenient plug-ins, such as the two Arrayed Waveguide Grating plug-ins that were actively used in the above mentioned MPW runs.
The biggest immediate benefit from deploying reusable building blocks in stable and mature processes, independent of whether it’s in a commercial foundry or an in-house fab, is that it improves yield and significantly brings down the costs of the chips as well as the associated development. This in itself is huge, because there are many applications, such as FTTH or data warehousing, where many millions of photonic chips can be deployed, but where the cost of optics has often still proven to be a barrier. But beyond bringing down the costs for high-volume applications, Photonics Design Automation also allows photonic chips to be introduced to a wider audience. There any many applications such as in bioscience, defense and fiber sensing, where volumes are smaller but that could benefit enormously from using integrated photonic chips. And PDA may just be the tool that now brings within reach those lower volume, but equally important, applications.
 Photonic Design Kits: http://www.phoenixbv.com/designkits
 M.K. Smit et al: ‘Generic foundry model for InP-based photonics,’
IET Optoelectronics, Vol 5(2011), No. 5, p. 187-194
 InP MPW brokering organisation: JePPIX -http://www.jeppix.eu
 TriPleX foundry: LioniX -http://www.lionixbv.com
 SOI MPW brokering organisation: ePIXfab http://www.epixfab.eu