
An alternative scheme has been conceived for packaging of silicon- based back-illuminated, back- side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in “Making a Back- Illuminated Imager With Back-Side Connections” (npo-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38.
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