G⁴FET Implementations of Some Logic Circuits

One circuit can be made to perform multiple logic functions.

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G⁴FETs and described below. These logic circuits are intended to serve as prototypes of more- complex advanced programmable-logic-device- type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G⁴FETs is such that fewer discrete components are needed to perform a given logic function in G⁴FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G⁴FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in “G⁴FETs as Universal and Programmable Logic Gates” (npo-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44.

A G⁴FET can be characterized as an accumulation-mode silicon- on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G⁴FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G⁴FETs.

The present G⁴FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G⁴FET. The side gates (JG1 and JG2) are used to linearly modulate the threshold voltage of the G⁴FET, thereby modulating the switching threshold voltage of the inverter. By judiciously selecting the design and operational parameters that affect the switching threshold voltage, the inverter can be made to function as a quaternary down literal converter. (The term “down literal converter” denotes a circuit that performs a function, known as the down literal function, that is the fundamental element in multi-valued logic.) Hence, the adjustable-threshold inverter can be made a basic building block of quaternary logic circuits.

The real-time-reconfigurable logic gate can be realized, in a circuit partly resembling the adjustable-threshold inverter, by applying the logic input signals to JG1 and JG2 and connecting the input terminal of what would otherwise be the inverter to a constant reference voltage (that is, making V_in a constant voltage). The number of transistors in this circuit is smaller than in a classical CMOS circuit that performs an equivalent logic function. The same hardware can be made to form any of three different functions: Depending on the value of V_in, the function is disabled output (V_out = V_DD or 0), the NOR of the logic levels represented by V_JG1 and V_JG2, or the NAND of the logic levels represented by V_JG1 and V_JG2.