Process for Patterning Indium for Bump Bonding
- Saturday, 01 December 2012
An innovation was created for the Cosmology Large Angular Scale Surveyor for integration of low-temperature detector chips with a silicon backshort and a silicon photonic choke through flip-chip bonding. Indium bumps are typically patterned using liftoff processes, which require thick resist. In some applications, it is necessary to locate the bumps close to high-aspect-ratio structures such as wafer through-holes. In those cases, liftoff processes are challenging, and require complicated and time-consuming spray coating technology if the high-aspect-ratio structures are delineated prior to the indium bump process. Alternatively, processing the indium bumps first is limited by compatibility of the indium with subsequent processing. The present invention allows for locating bumps arbitrarily close to multiple-level high-aspect-ratio structures, and for indium bumps to be formed without liftoff resist.The process uses the poor step coverage of indium deposited on a silicon wafer that has been previously etched to delineate the location of the indium bumps. The silicon pattern can be processed through standard lithography prior to adding the high-aspect-ratio structures. Typically, high-aspect-ratio structures require a thick resist layer so this layer can easily cover the silicon topography. For multiple levels of topography, the silicon can be easily conformally coated through standard processes. A blanket layer of indium is then deposited onto the full wafer; bump bonding only occurs at the high points of the topography.
This work was done by Kevin Denis of Goddard Space Flight Center. GSC-16386-1
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