Silicon Alignment Pins: An Easy Way To Realize a Wafer-to-Wafer Alignment
- Created: Sunday, 01 December 2013
- NASA’s Jet Propulsion Laboratory, Pasadena, California
Etched pockets and silicon pins are used to align two wafers together.
Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers.
Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved.
A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together. Each silicon piece is patterned with the pockets on both sides of the wafer, front and back, which are then etched down to ≈130μm.
Meanwhile, the silicon pins are etched in a 200-μm thick wafer. By etching a Cshaped pin, the pin can be compressed to fit into the alignment pocket by an appropriate choice of the pin wall thickness. When released, the pin expands to fill the pocket. A tight fit is ensured by choosing the relaxed pin diameter to be greater than the pocket diameter. This approach reduces the misalignment tolerance to the positional variation between the photolithographically defined pockets, which is typically under 3μm.
During assembly, the silicon compression pins are placed on the etched pockets of the first wafer, and the wafer to be aligned will find the right location using its own “back” etched pockets. The two wafers are therefore quickly and easily aligned. If more wafers need to be stacked, one can place additional layers, each time using the pins and the etched pockets as alignment features.
Using this method, one can align several wafers, if needed, by only handling and aligning two wafers at a time. Also, for accurate and tight alignments, the tolerances can be chosen down to only 1 μm by using more accurate lithography.
In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:
Innovative Technology Assets Management
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Pasadena, CA 91109-8099