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Fabrication of Buried Nanochannels From Nanowire Patterns

Sacrificial nanowires are buried, then etched away to form buried channels.

A method of fabricating channels having widths of tens of nanometers in silicon substrates and burying the channels under overlying layers of dielectric materials has been demonstrated. With further refinement, the method might be useful for fabricating nanochannels for manipulation and analysis of large biomolecules at single-molecule resolution. Unlike in prior methods, burying the channels does not involve bonding of flat wafers to the silicon substrates to cover exposed channels in the substrates. Instead, the formation and burying of the channels are accomplished in a more sophisticated process that is less vulnerable to defects in the substrates and less likely to result in clogging of, or leakage from, the channels.

In this method, the first step is to establish the channel pattern by forming an array of sacrificial metal nanowires on an SiO2-on-Si substrate. In particular, the wire pattern is made by use of focused-ion-beam (FIB) lithography and a subsequent metallization/ lift-off process. The pattern of metal nanowires is then transferred onto the SiO2 layer by reactive-ion etching, which yields sacrificial SiO2 nanowires covered by metal. After removal of the metal covering the SiO2 nanowires, what remains are SiO2 nanowires on an Si substrate.

Plasma-enhanced chemical vapor deposition (PECVD) is used to form a layer of a dielectric material over the Si substrate and over the SiO2 wires on the surface of the substrate. FIB milling is then performed to form trenches at both ends of each SiO2 wire. The trenches serve as openings for the entry of chemicals that etch SiO2 much faster than they etch Si. Provided that the nanowires are not so long that the diffusion of the etching chemicals is blocked, the sacrificial SiO2 nanowires become etched out from between the dielectric material and the Si substrate, leaving buried channels. At the time of reporting the information for this article, channels 3 μm long, 20 nm deep, and 80 nm wide (see figure) had been fabricated by this method.

This work was done by Daniel Choi and Eui-Hyeok-Yang of Caltech for NASA’s Jet Propulsion Laboratory. For more information, download the Technical Support Package (free white paper) at www.techbriefs.com/tsp under the Manufacturing & Prototyping category. In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:

Innovative Technology Assets Management
JPL
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
(818) 354-2240
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Refer to NPO-30839, volume and number of this NASA Tech Briefs issue, and the page number.

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