Analysis of On-Chip Heat Distribution in the Design of RF Power Detectors and Transistor Arrays

The simulation of electromagnetic (EM) and thermal properties of semiconductor and substrate materials has been demonstrated to be particularly helpful in the optimization of the design of Monolithic Micro wave Integrated Circuit (MMIC) power amplifier (PA) modules. Various design challenges, however, have to be dealt with in specific ways, and may require efficient approaches that accommodate reasonable approx imations in the development and troubleshooting phases. EM and heat transfer analysis at the semiconductor device structure level allows building accurate models for simulation tools.

In a time-constrained development environment, or for the training of highly qualified personnel, there is also a need for an approach that allows the designer to start with a simplified but efficient characterization of the EM and heat transfer effects at circuit building blocks level, and with the option of gradually including various structural elements towards a complete physical representation of the system under test.

COMSOL Multiphysics™ software was used in a design example that involved the need for estimating the effects of temperature on on-chip RF power detectors, given the RF power transistor array geometry.

Optimizing the performance matching between on-chip transistor- based RF power detectors may have a big impact on circuit behavior in some MMIC designs. The NPN HBT transistor used in this design typically offers base-to-emitter voltages (VBE) that vary by about -1.2mV/ºC. Therefore, in an envelope comparator circuit using strongly NPN-based nonlinear envelope detectors that deliver a feedback error signal in the order of a few millivolts only, a difference of several degrees between the two detectors may impair the feedback error correction process, even if sophisticated compensation circuit techniques are used.

Power Detectors and RF Transistor Array Design

The first IC, which includes two NPN transistor-based power detectors, is shown in Figure 1(a), together with an enlarged view of the detector area. Note that in this design, a very conservative approach of placing the two detectors as close as possible for matched performances has been used, with the goal of obtaining as symmetrical EM coupling and heat transfer as possible. The second IC, which includes the RF power transistor array, is shown in (b).

In the logical extension of merging the two designs on a single GaAs HBT chip, an optimization of the location of the two detectors needs to be performed. The conservative approach of placing the two detectors as close as possible might not be the best solution, because it requires the routing of the output signal towards the input section, which may affect stability and translate into sacrificing RF performances (this becomes even more severe at millimeter wave frequencies); and signal integrity in the input detector branch and/or in the output detector branch might be degraded (e.g. due to EM coupling from other signal traces on the chip) in trying to constrain the design of the layout in order to meet the requirement of having the two detectors very close to each other.