Wafer-Level Membrane-Transfer Process for Fabricating MEMS

This process is well suited for structures fabricated on dissimilar substrates.

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectro- mechanical systems (MEMS) that have been fabricated on dissimilar substrates.

Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two wafer-level structures to be integrated with each other are indium-bump-bonded together; this is advantageous in that it produces less (in comparison with other bonding techniques) stress during bonding of structures formed on two dissimilar wafers. Moreover, unlike in some older membrane-transfer processes, there is no incidental release of HF from the final structure — an advantage when indium, aluminum, or another soft metal is used for bonding.

This process was demonstrated by applying it to the joining of (1) a corrugated polycrystalline silicon (polysilicon) membrane that had been fabricated by patterning and etching on a silicon-on- insulator (SOI) wafer with (2) a silicon substrate. A 1-μm thick corrugated polysilicon membrane has been transferred onto an electrode wafer to show the feasibility of the proposed technique. The transferred membrane with underlying electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 °C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 °C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF₆ plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF₆ plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform (±0.1 μm across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

This work was done by Eui-Hyeok Yang and Dean Wiberg of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Manufacturing category.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to
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Refer to NPO-21088, volume and number of this NASA Tech Briefs issue, and the page number.