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Deployable Antenna Circuit Board Material Design and Fabrication Process

This technology has applications in solar arrays for small satellites. NASA’s Jet Propulsion Laboratory, Pasadena, California The Integrated Solar Array and Reflectarray (ISARA) antenna requires a rugged circuit board material that will meet the following requirements: (1) remains sufficiently flat over the required operating temperature range with solar cells mounted, and under full solar illumination, including heat dissipation due to ≈30% efficiency solar cells; (2) provides a sufficiently high-quality RF-grade circuit board material needed to print the reflectarray antenna; (3) is sufficiently thin (<2.5 mm) to fit within the available stowage volume; and (4) has low mass density (≈5 kg/m2).

Posted in: Briefs, TSP, Electronics

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Moon Tours Android

NASA’s Jet Propulsion Laboratory, Pasadena, California This Android app provides a native interface to the Lunar Mapping and Modeling Portal’s (LMMP) lunar data archive and analysis tools. It complements the iOS app previously released, incorporating a very similar feature set. Both apps contain a subset of the functionality available in the desktop/Web version. Compared to the iOS version of the LMMP, the Android version provides the additional tools necessary to perform elevation analysis and perimeter/area measurements.

Posted in: Briefs, TSP, Electronics & Computers

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Development of a Multi-User Modem for Space Telecommunications

This technology has applications in the cellphone industry. NASA’s Jet Propulsion Laboratory, Pasadena, California Efficient support of planetary surface missions typically requires an orbiting asset that acts as a relay point to/from Earth. Orbital relay passes are normally 5 to 15 minutes in duration over any specific landed site. When multiple landed assets are co-located or near-located in the same coverage circle of a single relay orbiter, their telecom relay support opportunities will overlap. This will be the case with cooperative lander missions, a lander-rover operations pair, distributed intelligent lander missions, and future deployment of multiple equipment components for support of complex sample return or manned operations. In these situations, the capability of simultaneous support to multiple landers is very valuable for mission performance and operations flexibility. This technology work enables simultaneous telecom support to multiple landers (Mars, Titan, Europa), and provides single-radio, multi-mode support to Entry, Descent & Landing (EDL) and emergency operations (e.g., demodulation + Open Loop Recording).

Posted in: Briefs, TSP

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Wire Bonding to Pads in Tilted Planes

This technique can be used in industries where devices need to be made smaller and lighter, such as medical, aerospace, automotive, and military. NASA’s Jet Propulsion Laboratory, Pasadena, California Scientific imaging arrays need to have their individual imaging elements arranged in a close-spaced mosaic. The typical single imaging element is a silicon chip mounted on a larger support frame. This excess area of the support frame takes away valuable imaging space from the mosaic. This appears as a grid of black (no data) in the overall mosaic image. Making the support frame smaller makes the amount of lost data smaller, and the imaging elements can be spaced more closely together. Eliminating the support frame altogether brings the imaging elements even closer. This is referred to as four-side buttable.

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cFE/CFS Evolution for Multicore Platforms

Goddard Space Flight Center, Greenbelt, Maryland This effort ports the Core Flight Executive (cFE)/Core Flight System (CFS) flight software architecture to multicore processor platforms, and provides mission developers with a common, flightready, flexible software environment that supports single, multi-processor, and multicore systems. Currently the cFE/CFS only supports single-core processors.

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FPGA Reconfiguration with Accelerated Bitstream Relocation

Goddard Space Flight Center, Greenbelt, Maryland Partial bitstream relocation (PBR) on field programmable gate arrays (FPGAs) is a technique to re-scale parallelism of accelerator architectures at run time and enhance fault tolerance. PBR techniques have focused on reading inactive bitstreams stored in memory, on-chip or off-chip, whose contents are generated for a specific partial reconfiguration region (PRR) and modified on demand for configuration into a PRR at a different location.

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Real-Time LiDAR Signal Processing FPGA Modules

Goddard Space Flight Center, Greenbelt, Maryland A scanning LiDAR, by its inherent nature, generates a great deal of raw digital data. To generate 3D imagery in real time, the data must be processed as quickly as possible. One method of discerning time-of-flight of a laser pulse for a LiDAR application is correlating a Gaussian pulse with a discretely sampled waveform from the LiDAR receiver.

Posted in: Briefs, TSP

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