Property Value
Name Error-Detecting Counters for FPGA and ASIC State Machines
Description A scheme has been found for protecting critical counters in FPGAs and ASICs from SEUs using monotonicity checking. This scheme involves very little overhead, in fact just a 2 bit auxiliary counter is used at minimum, or just 2 extra states in a state machine.
Filesize 101.51 kB
Last updated on 02/01/2008 10:48

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