| Software-Reconfigurable Processors for Spacecraft |
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| NASA’s Jet Propulsion Laboratory, Pasadena, California | |
| Jul 01 2005 | |
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advertisement: A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven inflight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs). This work was done by Allen Farrington, Andrew Gray, Bryan Bell, Valerie Stanton, Yong Chong, Kenneth Peters, Clement Lee, and Jeffrey Srinivasan of Caltech for NASA’s Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Electronics/ Computers category. This Brief includes a Technical Support Package (TSP).
Software-Reconfigurable Processors for Spacecraft (reference NPO-30357) is currently available for download from the TSP library. Login first to download.
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