To illustrate the throughput advantage that parallel testing offers, it is helpful to contrast it with the traditional sequential approach to parametric test (Figure 1). The total test time for an individual TEG is approximately the sum of the test times for the individual test devices, plus any delays due to switching latencies, which can be significant.

Ideally, parallel tests start simultaneously and chain together with no delays in each thread, but realistically, there are slight delays between the start times of each test sequence due to latencies in the prober, controller, and parametric tester. In sequential mode, tests run consecutively, synchronized so that the start of the next test sequence begins upon the conclusion of the prior sequence.

Figure 2a. Schematic of sequential mode testing.

Figure 2b. Schematic of parallel mode testing.

Devices tested in parallel may be all the same type (homogenous) or different types (heterogeneous). For example, two transistors, one resistor, and one diode could potentially be measured independently in parallel by performing different connect-force-measure sequences on all four devices simultaneously. Figures 2a and 2b illustrate the difference between sequential mode and parallel mode testing within a TEG.

Figure 2 illustrates how the parallel mode test sequence maximizes use of available instrument resources (SMUs, signal generators, etc.). Parallel test has the potential for greatly reducing test times or allowing the collection of more data within a given time frame.