Taking Advantage of Parallel Parametric Testing

Note that we are discussing only parallel testing at the wafer level, not of packaged devices. Although both types of parallel testing use a similar testing strategy (i.e., the use of multiple SMUs operating asynchronously to reduce total test time), there are obvious differences. The most significant one, other than the size and cost of the test hardware itself, is that functional tests of packaged devices are largely immune to the parasitic capacitances between wafer devices under test that can interfere with parametric test accuracy, whether tests are performed sequentially or in parallel.

Parallel Test Strategies

For mature wafer processes and test cells, the most practical way to get involved in parallel testing is to start with existing TEGs and change the test sequencing (Figure 2). Typically, this would require analysis of both the TEG and the test sequence to identify opportunities for reordering or regrouping existing tests on heterogeneous structures in a way that minimizes the time needed for switching between test pads. This represents the fastest, surest way to achieve significant throughput improvements with a relatively limited investment in analysis effort, new software, and test sequence modifications.

There may be cases where a more extensive overhaul of the test process is justified to achieve larger gains in test throughput. This demands much more extensive analysis of both the test sequence and the TEG itself, because it requires significant changes to both. Typically, this also requires a number of new reticles that must be designed, created, and validated to allow parallel testing of more structures within the TEG. This strategy may also require changes to the probe card design, as well as the installation of additional source-measure instrumentation. The expense and time required for these changes must be weighed against the expected cost reductions and benefits from more extensive data collection.

During technology development for new products, it’s relatively inexpensive to design new TEGs in a way that maximizes the number of structures that can be tested in parallel. Given that there are no existing reticles or test sequences that must be replaced, there’s no existing testing process to disrupt. While this offers the highest potential for payback in terms of throughput, it’s wiser not to try implementing parallel test for the first time on a new product, when there are many other priorities to consider while trying to ramp up production. Instead, the knowledge gained from first implementing parallel test on mature processes can be applied to the process of implementing it on new products later. Parametric test vendors can also provide enormous assistance by reviewing test structures and algorithms, which may make it possible to ramp parallel test technology significantly faster.

Parallel Test Advantages and Benefits

The most obvious advantage of parallel test is its impact on the parametric tester’s COO. The largest “lever” on COO for a process or metrology tool is system throughput. Since parallel test can increase throughput dramatically, it has a proportional effect in driving down COO. Users have documented throughput increases due to parallel test by factors ranging from 1.05X to 3.9X. The degree of throughput improvement that a particular test cell can achieve depends on a variety of factors, which include:

• Existing test structure and pad layout. In order to minimize precious wafer real estate devoted to TEGs, test structures typically have been designed with shared gate pads, which can make it impossible to test certain structures in parallel.
• Specific combination of test structures within the TEG. Consider, for example, a test structure made up of an array of transistors, all with a single shared gate pad. Complete characterization of these devices in parallel testing would be impossible with such a structure. Conversely, a resistor network would likely allow testing of all the resistors in parallel because such a structure would have a pad at every node in the network, allowing the tester to source current across the network, then measure voltage drop at each node.
  
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