| Taking Advantage of Parallel Parametric Testing |
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| Jul 31 2007 | |
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A more likely scenario is a TEG that includes at least one capacitor, one resistor, one diode, and one transistor. Although some of these test structures may share pads, some level of parallel testing is still achievable. On the other hand, C-V measurements are typically performed sequentially, largely because few testers are equipped with more than one C-V meter. There also are lingering concerns about the potential for C-V measurements to create parasitic coupling with nearby structures or probe tips if performed in parallel with other measurements. Parallel test can be a good option for plants with limited make-up test capacity and that lack the resources and/or floor space to add another test cell. By allowing more efficient use of existing test hardware, parallel test can often eliminate the need for additional test cells, or reduce the number of test cells needed when equipping a new plant. Parallel test users have reported a variety of other benefits that helped reduce their overall cost of parametric test:
In addition to parallel test, adaptive testing has the potential for increasing test throughput. Results-based adaptive testing allows programming the tester to increase or decrease the number of sites tested and the number of tests performed on a wafer based on the results of previous measurements. If the results from previous sites are acceptable, the number of sites and/or tests can be reduced, thereby increasing throughput when testing good wafers. This article was written by Randall Lee, Senior Industry Market Manager at Keithley Instruments in Cleveland, OH. More information on parallel test can be found in “Parallel Test Technology” published by Keithley. Visit Here to obtain a free copy of the handbook. |



















