The production of many electronic devices begins with wafer processing. In addition to complementary metal oxide semiconductor (CMOS) integrated circuits (ICs), this can include such diverse devices as radio frequency (RF) components based on III-V compounds and chemical detectors based on carbon nanotube (CNT) field effect transistors (FETs). In both R&D and production applications, there is a great deal of effort devoted to increasing device test throughput in order to shorten the time to market and reduce costs.

Figure 1. Comparison of elapsed times between sequential and parallel testing of four DUTs. The sequential test time (ts) is approximately 3.8 times longer than the parallel test time (tp).

Parallel Test Process

The shortest, simplest definition of parallel parametric test is that it’s an emerging strategy for wafer-level parametric testing that involves concurrent execution of multiple tests on multiple scribe line test structures. It offers a relatively inexpensive way to increase throughput, thereby lowering the cost of ownership (COO) significantly. Just as important, parallel testing can address the growing need to perform more tests on the same structures in less time as device scaling increases the randomness of failures.

In most cases, the structures being tested in parallel are in a single Test Element Group (TEG) located in a wafer scribe line. Even among leading edge manufacturers, very few have progressed to the point of testing structures in different TEGs simultaneously. Implementing this strategy involves using the tester’s controller to interleave execution of the multiple tests in a way that maximizes the use of processing time and test instrumentation capacity that would otherwise be standing idle. When the design of test structures allows, this “multi-threaded” approach to test sequencing reduces the execution time for multiple tests on multiple structures to little more than the time needed to execute the longest test in the sequence.