Electronic Switch Arrays for Managing Microbattery Arrays

NASA’s Jet Propulsion Laboratory

Friday, August 01 2008

Array circuitry is dynamically configured to optimize performance and disconnect defective elements.

Integrated circuits have been invented for managing the charging and discharging of such advanced miniature energy-storage devices as planar arrays of microscopic energy- storage elements [typically, microscopic electrochemical cells (microbatteries) or microcapacitors]. The architecture of these circuits enables implementation of the following energy- management options:

• Dynamic configuration of the elements of an array into a series or parallel combination of banks (subarrays), each array comprising a series or parallel combination of elements;
• Direct addressing of individual banks for charging and/or discharging; and
• Disconnection of defective elements and corresponding reconfiguration of the rest of the array to utilize the remaining functional elements to obtain the desired voltage and current performance.

One of the reasons for fabricating microbattery and microcapacitor arrays is that the array form affords partial immunity to defects in individual energy-storage elements. Defective energy-storage elements act as loads on the functional ones, thereby reducing the capacity of an overall array. By enabling the disconnection of defective elements and reconfiguration of the rest of the array, the present invention offers practical means to realize this partial immunity. In addition, the invention provides for interrogating individual cells and banks in the array and charging them at the current-vs.-time or voltage-vs.-time characteristics needed for maximizing the life of the array.

An integrated circuit according to the invention consists partly of a planar array of field-effect transistors that function as switches for routing electric power among the energy-storage elements, the power source, and the load (see figure). To connect the energy-storage elements to the power source for charging, a specific subset of switches is closed; to connect the energy- storage elements to the load for discharging, a different specific set of switches is closed.

Also included in the integrated circuit, but omitted from the figure for the sake of simplicity, is circuitry for monitoring and controlling charging and discharging. The control and monitoring circuitry, the switching transistors, and interconnecting metal lines are laid out on the integrated-circuit chip in a pattern that registers with the array of energy-storage elements. There is a design option to either (1) fabricate the energy-storage elements in the corresponding locations on, and as an integral part of, this integrated circuit; or (2) following a flip-chip approach, fabricate the array of energy-storage elements on a separate integrated-circuit chip and then align and bond the two chips together.

This work was done by Mohammad Mojarradi, Mahmoud Alahmad, Vinesh Sukumar, Fadi Zghoul, Kevin Buck, Herbert Hess, Harry Li, and David Cox of Caltech for NASA’s Jet Propulsion Laboratory.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:

Innovative Technology Assets Management
JPL
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
(818) 354-2240
E-mail: This e-mail address is being protected from spambots. You need JavaScript enabled to view it

Refer to NPO-43318, volume and number of this NASA Tech Briefs issue, and the page number.