Bit-Serial Adder Based on Quantum Dots

NASA's Jet Propulsion Laboratory, Pasadena, California

Wednesday, January 01 2003 Again, for reasons too complex to describe here, in order to ensure accuracy and timeliness of the output of a QCA array, it is necessary to resort to an adiabatic switching scheme in which the QCA array is divided into subarrays, each controlled by a different phase of a multiphase clock signal. In this scheme, each subarray is given time to perform its computation, then its state is frozen by raising its interdot potential barriers and its output is fed as the input to the successor subarray. The successor subarray is kept in an unpolarized state so it does not influence the calculation of preceding subarray. Such a clocking scheme is consistent with pipeline computation in the sense that each different subarray can perform a different part of an overall computation. In other words, QCA arrays are inherently suitable for pipeline and, moreover, systolic computations. This sequential or pipeline aspect of QCA would be utilized in the proposed bit-serial adders.

The design of the proposed bit-serial adder incorporates a two-step innovation: (1) the design of an efficient QCA-based circuit that would function as a full adder, and (2) the design of QCA-based feedback loop with proper clocking that would enable the full adder to perform bit-serial addition. The full adder (see Figure 1) would contain three inverter gates and five majority gates. Given two input bits (A and B) and one previous carry bit (C_i–1), this circuit would generate a sum bit (S) and a new carry bit (C_i).

A bit-serial adder would perform the addition operation on two sequences of input bits (a_i and b_i for i = 1 to n) to generate a sequence of sum bits (S_i for i = 1 to n + 1). To be able to perform the addition operation, the adder would have to be capable of storing the intermediate carry bits. A feedback loop could be used to effect such storage.

Figure 2 schematically depicts a bit-serial adder containing three majority gates and two inverter gates. This circuit could, optionally, be used as a full adder, in which role it would be more efficient, relative to the adder of Figure 1, in that it would contain fewer gates. The main advantage of the circuit of Figure 2 is that by use of suitable multiphase clocking, one could cause part of the circuit to act as a feedback loop for temporary storage of intermediate carry bits, thus enabling bit-serial addition. The ability of this circuit to perform bit-serial addition has been verified by computer simulation. However, several obstacles to practical implementation of a QCA-based bit-serial adder that could function without error at room temperature must still be overcome.

This work was done by Amir Fijany, Nikzad Toomarian, Katayoon Modarress, and Matthew Spotnitz of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Computers/Electronics category. NPO-20869.