Miller-Jogging for Synthesizer Lock Algorithm Extension

NASA’s Jet Propulsion Laboratory, Pasadena, California The University of California Los Angeles (UCLA) has developed a wide range of CMOS (complementary metal–oxide–semiconductor) phase lock loop (PLL) chips with self-healing/self-calibration capabilities, allowing them to adapt, on the fly, to changes in temperature and other environment parameters. All CMOS PLLs typically have three major settings that self-healing and calibration can adjust: VCO (voltage controlled oscillator) coarse tuning, divider tuning, and CML (current mode logic) tuning. Previous work done at UCLA uses these “knobs” or settings exclusively to self-lock a PLL. Locking criteria is established by monitoring the control voltage with an analog-to-digital converter (ADC) to see if the PLL loop is settled in the middle of the range (locked), or sitting at the ground or supply (unlocked).

Posted in: Briefs, Electronics, Electronics & Computers


Deployable Antenna Circuit Board Material Design and Fabrication Process

This technology has applications in solar arrays for small satellites.The Integrated Solar Array and Reflectarray (ISARA) antenna requires a rugged circuit board material that will meet the following requirements: (1) remains sufficiently flat over the required operating temperature range with solar cells mounted, and under full solar illumination, including heat dissipation due to ≈30% efficiency solar cells; (2) provides a sufficiently high-quality RF-grade circuit board material needed to print the reflectarray antenna; (3) is sufficiently thin (<2.5 mm) to fit within the available stowage volume; and (4) has low mass density (≈5 kg/m2).

Posted in: Briefs, TSP, Electronics, Electronics & Computers


Implementing High Density Embedded Computing (HDEC) Solutions

High Density Embedded Computing solutions are solving large data throughput needs in signals intelligence, ground control, and homeland security applications. This guide focuses on how to efficiently implement these technologies including the expanded availability of native PCI Express 3.0 interfaces.

Posted in: White Papers, Defense, Electronics, Electronics & Computers, Electronics & Computers, Software


Full-Wave Matching Circuit Optimization Shortens Design Iterations

Full-wave matching circuit optimization (FW-MCO) is a new technology introduced by Remcom, which combines full wave 3D EM simulation and circuit optimization to solve an age-old RF problem:determining which component values provide the desired match for a given matching network layout.

Posted in: White Papers, Communications, Electronics, Electronics & Computers, Electronics & Computers, Software


Stencil-less Jet Printing for PCB Assembly

Imagineering, Inc. introduces stencil-less Jet Printing to facilitate quick turn around Printed Circuit Board Assembly.

Posted in: White Papers, Electronics, Electronics & Computers


Full RF Signal Chains from 0 Hz to 110 GHz

Analog Devices (ADI) has expanded its RF capabilities in the full signal chain, including companion products, in the full bandwidth from 0 Hz to 110 GHz.This white paper provides examples of the wider frequency spectrum covered by ADI, and explains that true DC is important. Off signal chain performance is also critical, and this paper shows how low-noise, high-stability control and power components are important to overall RF signal performance.

Posted in: White Papers, Electronics, Semiconductors & ICs, Data Acquisition, Sensors, Test & Measurement


Microelectronics Package for Extreme Environments

Anaren’s MSK Products Division designed, built, and tested a high-temperature, co-fired ceramic (HTCC) electronics package for use in oil and gas drilling that proved Anaren’s ability to push the boundaries for developing microelectronics packages to survive in difficult high-temperature environments.

Posted in: White Papers, White Papers, Aeronautics, Defense, Electronics, Electronics & Computers


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