Semiconductors & ICs

Vertical Isolation for Photodiodes in CMOS Imagers

Diffusion cross-talk would be reduced substantially. In a proposed improvement in complementary metal oxide/semi con ductor (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/ semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

Posted in: Briefs, Semiconductors & ICs, Imaging and visualization


Onboard Data Processor for Change-Detection Radar Imaging

This system could be used to map earthquakes, landslides, floods, and wildfires. A computer system denoted a change-detection onboard processor (CDOP) is being developed as a means of processing the digitized output of a synthetic-aperture radar (SAR) apparatus aboard an aircraft or spacecraft to generate images showing changes that have occurred in the terrain below between repeat passes of the aircraft or spacecraft over the terrain. When fully developed, the CDOP is intended to be capable of generating SAR images and/or SAR differential interferograms in nearly real time. The CDOP is expected to be especially useful for understanding some large-scale natural phenomena and/or mitigating natural hazards: For example, it could be used for near-real-time observation of surface changes caused by floods, landslides, forest fires, volcanic eruptions, earthquakes, glaciers, and sea ice movements. It could also be used to observe such longer-term surface changes as those associated with growth of vegetation (relevant to estimation of wildfire fuel loads).

Posted in: Briefs, TSP, Semiconductors & ICs


HEMT Amplifiers and Equipment for Their On-Wafer Testing

Power levels in CPW circuits can be measured without packaging. Power amplifiers comprising InP-based high-electron-mobility transistors (HEMTs) in coplanar-waveguide (CPW) circuits designed for operation at frequencies of hundreds of gigahertz, and a test set for on-wafer measurement of their power levels have been developed. These amplifiers utilize an advanced 35-nm HEMT monolithic microwave integrated-circuit (MMIC) technology and have potential utility as local- oscillator drivers and power sources in future submillimeter-wavelength heterodyne receivers and imaging systems. The test set can reduce development time by enabling rapid output power characterization, not only of these and similar amplifiers, but also of other coplanar-waveguide power circuits, without the necessity of packaging the circuits.

Posted in: Briefs, Semiconductors & ICs, Amplifiers, Integrated circuits, Test procedures


On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

Compact, low-power, electronically tunable submillimeter-wave local oscillators are now feasible. The world’s first silicon- based complementary metal oxide/semi- conductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power- consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter-wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog-to-digital converters, and advanced microprocessors.

Posted in: Briefs, TSP, Semiconductors & ICs


Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

Semiconductor junctions are relocated away from Si/SiO2 interfaces. Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated- circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal- handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

Posted in: Briefs, Semiconductors & ICs, Imaging and visualization, Integrated circuits, Semiconductor devices, Performance upgrades


Low-Temperature Supercapacitors

Electrolyte compositions are designed to extend the low-temperature operational limit.An effort to extend the low-temperature operational limit of supercapacitors is currently underway. At present, commercially available non-aqueous supercapacitors are rated for a minimum operating temperature of –40 °C. A capability to operate at lower temperatures would be desirable for delivering power to systems that must operate in outer space or in the Polar Regions on Earth.

Posted in: Briefs, TSP, Semiconductors & ICs, Ultracapacitors and supercapacitors, Performance upgrades


MEMS/ECD Method for Making Bi₂₋ₓSbₓTe₃ Thermoelectric Devices

Devices containing diverse materials in complex three-dimensional shapes can be fabricated.A method of fabricating Bi2–xSbxTe3-based thermoelectric microdevices involves a combination of (1) techniques used previously in the fabrication of integrated circuits and of microelectromechanical systems (MEMS) and (2) a relatively inexpensive MEMS-oriented electrochemical- deposition (ECD) technique. The devices and the method of fabrication at an earlier stage of development were reported in “Sub milli meter-Sized Bi2–xSbxTe3 Thermoelectric Devices” (NPO-20472), NASA Tech Briefs, Vol. 24, No. 5 (May 2000), page 44. To recapitulate: A device of this type generally contains multiple pairs of n- and p-type Bi2–xSbxTe3 legs connected in series electrically and in parallel thermally. The Bi2–xSbxTe3 legs have typical dimensions of the order of tens of microns. Metal contact pads and other non-thermoelectric parts of the devices are fabricated by conventional integrated-circuit and MEMS fabrication techniques. The Bi2–xSbxTe3 thermoelectric legs are formed by electrodeposition, through holes in photoresist masks, onto the contact pads.

Posted in: Briefs, Semiconductors & ICs


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