Semiconductors & ICs

Bending Light with a Tiny Chip

Imagine that you are in a meeting with coworkers or at a gathering of friends. You pull out your cell phone to show a presentation or a video on YouTube. But you don't use the tiny screen; your phone projects a bright, clear image onto a wall or a big screen. Such a technology may be on its way, thanks to a new light-bending silicon chip developed by researchers at Caltech.

Posted in: News, Board-Level Electronics, Electronic Components, Optical Components, Optics, Photonics


Sub-Nanosecond, Compact, Low-Power Time-Interval Measurement

This innovation is a sub-nanosecond time-interval measurement that is compact and inexpensive, implemented in a field-programmable gate array (FPGA). Currently, high-speed count ers or semi-custom or custom ASICs (application specific integrated circuits) are used for time-interval measurements. They are not nearly as powerful for automatic delay control for the environment (manufacturing, temperature, voltage, aging, and radiation).

Posted in: Electronics & Computers, Briefs, TSP


CoolSPICE: SPICE Simulator for Cryogenic Electronics

Accurate assessment of circuits at cold temperatures is extremely difficult due to lack of models and tools that can simulate circuit behavior at cryogenic temperatures. A library of cryogenic temperature models was built, as well as a circuit simulator that can use those models and simulate complex circuits at temperatures as low as 4 K.

Posted in: Software, Briefs, TSP


Metal-Assisted Fabrication of Biodegradable Porous Silicon Nanostructures

Silicon nanostructures are fabricated from single-crystal silicon by an electroless chemical etch process. Porous silicon nanowires are fabricated by two-step, metal-assisted electroless chemical etching of p-type or n-type silicon wafers. This method, in combination with nanolithography or nanopatterning, can be applied to fabricate porous silicon nanostructures of different shapes and sizes, such as nanorods, nanobelts, nanostrips, and nanochains. The specific resistivity of the silicon substrate, and composition of the etching solution, determine the porosity and pore size or lack thereof of the resulting nanostructures. Silicon doping, type of metal catalyst, concentrations of H2O2, and solvent all affect the formation of porous nanostructures at various resistivity ranges of silicon. A phase diagram summarizing the relation of porosification and doping, metal, concentrations of H2O2, and solvent can be generated. In this innovation, high-aspect-ratio porous silicon nanostructures, such as those previously mentioned, were fabricated from single-crystal silicon by an electroless chemical etch process. A metal film, metal nanofeatures, or metal nanoparticles were coated on the silicon substrate first, and a solution of HF and hydrogen peroxide was then used to anisotropically etch the silicon to form the porous silicon nanostructures. Up to hundreds of micron-long high-aspect-ratio porous silicon nanostructures can be fabricated, and the patterns of the cross-section of porous silicon structures can be controlled by photolithography, nanolithography, or nanoparticle-assisted patterning. The porosity is related to the resistivity range of the silicon substrate, the metal catalysts, the chemical concentration, and the additive solvent. The fabricated porous silicon nanostructure is biodegradable, and the degradation time can be controlled by surface treatments. Porous silicon nanowires can be fabricated with a two-step process. A nanostructured metal layer can be deposited on a silicon substrate by an electroless chemical deposition or electrochemical deposition. This step determines the shape of the final nanowires. Alternatively, metal nanoparticles can be spun on the silicon surface to form a metal layer, or a metal layer can be physically or chemically deposited on the silicon through a nanopatterned mask. The metal-coated silicon can be etched in a solution of HF, water, and H2O2 to produce porous silicon nanowires. Solvent can be added to the solution to modulate the features of the porous silicon nanowires. This work was done by Mauro Ferrari, Xuewu Liu, and Ciro Chappini of the University of Texas Health Science Center at Houston for Johnson Space Center. For further information, contact the JSC Innovation Partnerships Office at (281) 483-3809. In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:   The University of Texas  Health and Science Center at Houston  Office of Technology Management  7000 Fannin Street, Suite 720  Houston, TX 77030 MSC-24690-1

Posted in: Briefs


Dual-Leadframe Transient Liquid Phase Bonded Power Semiconductor Module Assembly and Bonding Process

This module package and bonding process enable device operation at temperatures exceeding 400 °C. A high-temperature-capable widebandgap semiconductor power module package, coupled with a new high-temperature- capable bonding process (with an optimized assembly and manufacturing process), has been developed that, together, can allow device operation at temperatures exceeding 400 °C, with the potential for higher-temperature operation depending on the semiconductor device characteristics. The semiconductor module is an ultracompact, hybrid power module that uses double leadframes and direct lead-frame-to- chip transient liquid phase (TLP) bonding. The unique advantages include very high current-carrying capability, low package parasitic impedance, low thermomechanical stress at high temperatures, double-side cooling, and modularity for easy system-level integration. The new power module will have a very small form factor with 3 to 5× reduction in size and weight from the prior art, no failure-prone bond wires, and will be capable of operating from 450 to –125 °C.

Posted in: Briefs


Head-Mounted Display Embeds an Augmented Reality Chip

Researchers at the Korea Advanced Institute of Science and Technology (KAIST) developed K-Glass, a wearable, hands-free head-mounted display (HMD).Unlike virtual reality which replaces the real world with a computer-simulated environment, augmented reality (AR) incorporates digital data generated by the computer into the reality of a user. With the computer-made sensory inputs such as sound, video, graphics or GPS data, the user’s real and physical world becomes live and interactive. The AR processor has a data processing network similar to that of a human brain’s central nervous system. When the human brain perceives visual data, different sets of neurons, all connected, work concurrently on each fragment of a decision-making process; one group’s work is relayed to other group of neurons for the next round of the process, which continues until a set of decider neurons determines the character of the data. Likewise, the artificial neural network allows parallel data processing, alleviating data congestion and reducing power consumption significantly.   Source Also: Learn about a Volumetric 3D Display System with Static Screen.

Posted in: News


Flexible Microstrip Circuits for Superconducting Electronics

Improved wiring geometry should further reduce the size of the wiring while also reducing the crosstalk among wire pairs. Flexible circuits with superconducting wiring atop polyimide thin films are being studied to connect large numbers of wires between stages in cryogenic apparatus with low heat load. The feasibility of a full microstrip process, consisting of two layers of superconducting material separated by a thin dielectric layer on 5 mil (≈0.13 mm) Kapton sheets, where manageable residual stress remains in the polyimide film after processing, has been demonstrated. The goal is a 2-mil (≈0.051-mm) process using spin-on polyimide to take advantage of the smoother polyimide surface for achieving high-quality metal films. Integration of microstrip wiring with this polyimide film may require high-temperature bakes to relax the stress in the polyimide film between metallization steps.

Posted in: Briefs, TSP


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