When host testing is complete, the final version of the generated code can be used for production. If highly optimized or specialized code is required for deployment, this last implementation step can be done by hand. Whether automatically generated or hand-coded, the final implementation can be tested on the target hardware (microprocessor, DSP, or FPGA).

Implementing Model-Based Design

Figure 2. Receiver portion of the model partitioned with the high-speed fixed-point portion in yellowand the lower-speed, single precision floating-point portion in green. RF from actual GPS satellites iscaptured with a spectrum analyzer. This is now the data source for verifying the model with real-worlddata.
Given this background, let’s look at an example of how Model-Based Design could be used to develop a GPS receiver. The GPS system has been fully operational with 24 satellites in its constellation since 1994, and its use is ubiquitous. The example involves using code-division multiple access (CDMA) for time-delay measurement to yield range. All satellites share the same carrier frequency of 1.57542 GHz for civilian access, which has not changed in the past 30 years.

The design process starts with the creation of a system-level model of a GPS receiver from the written specification for a GPS physical layer. The model, shown in Figure 1, contains the transmitter, channel, receiver, and measurement visualization subsystems, and has numerous levels of hierarchy. The transmitter model introduces timing errors to test the receiver timing recovery control loop, while the channel model adds Doppler shift to test the receiver carrier tracking loop. Once the simulation of the design meets the required performance goals, the system-level model becomes an executable specification.

Next, the algorithm model can be partitioned into a portion that will reside in the FPGA and a portion that will reside in the floating-point DSP. For example, incoming I/Q data arriving at a rate of 8 million samples per section (MSPS) and passing through a root-raised cosine FIR filter is best suited for the FPGA. On the other hand, once the signal has been de-spread, the data rate is 1000 Hz, and can easily be handled by a DSP. After the receiver

model is working with floating-point arithmetic, the next step is to elaborate the model with fixed-point attributes that will be required for the FPGA partition.

Implementation on the FPGA can be automated at this point using the fixed-point model of the FPGA partition with tools such as Simulink HDL Coder or Xilinx System Generator. Then, using HDL simulators, it’s possible to verify that the implementation is functionally equivalent to the design model. Similarly, using the model of the DSP partition, the C code can be automatically generated by tools such as Real-Time Workshop Embedded Coder for deployment. Before integrating the C onto the DSP, it can be pulled back into the simulation environment and checked against the model to confirm functional equivalence, as was done with the HDL code. The last step is to deploy the HDL to the FPGA and the C to the DSP, and confirm that there are no errors introduced on the target hardware.

Using Model-Based Design, engineering teams developing advanced communications systems can collaborate in a common environment that enables them to capture the algorithm design as well as system-level effects of non-idealized hardware. As a result, the teams can optimize their designs through design exploration, identify design errors prior to implementation, and use modern commercial off-the-shelf (COTS) tools to automate much of the work.

This article was written by Jon Friedman, Aerospace and Defense Marketing Manager for The MathWorks, Natick, MA. For more information, visit http://info.hotims.com/28052-121.

« Start Prev 1 2 Next End»

The U.S. Government does not endorse any commercial product, process, or activity identified on this web site.