Semiconductors & ICs

High-Voltage-Input Level Translator Using Standard CMOS

High-voltage input circuitry would be combined with standard low-voltage CMOS circuitry.

A proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, “low” and “high” refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure.

Posted in: Briefs, TSP, Semiconductors & ICs, Integrated circuits, Integrated circuits, Semiconductors
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Small Microprocessor for ASIC or FPGA Implementation

A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions.

Posted in: Briefs, TSP, Semiconductors & ICs, Architecture, Computer software / hardware, Computer software and hardware, Integrated circuits, Architecture, Computer software / hardware, Computer software and hardware, Integrated circuits, Semiconductors
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Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 °C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory.

Posted in: Briefs, TSP, Semiconductors & ICs, Electronic equipment, Transistors, Electronic equipment, Transistors, Semiconductors
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Monitoring Digital Closed-Loop Feedback Systems

Designed-in test circuitry enables determination of performance margins and performance trends.

A technique of monitoring digital closed-loop feedback systems has been conceived. The basic idea is to obtain information on the performances of closed-loop feedback circuits in such systems to aid in the determination of the functionality and integrity of the circuits and of performance margins.

Posted in: Briefs, TSP, Semiconductors & ICs, Integrated circuits, Integrated circuits, Semiconductors, Performance tests
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Semiconductor Laser Technology Chosen for Space LIDAR

Single-frequency semiconductor laser
Redfern Integrated Optics (RIO)
Santa Clara, CA
408-970-3500
www.rio-inc.com

NASA has chosen Redfern Integrated Optics to further develop a single-frequency, narrow-linewidth semiconductor laser suitable for spaceflight operation. RIO’s external-cavity semiconductor laser technology is based on the hybrid integration of an indium phosphide (InP) gain chip and a planar lightwave circuit (PLC) with Bragg gratings. Packaged in a standard 14-pin compact “butterfly” package, the laser is characterized by a single-frequency output in the 1550-nm spectral region with a linewidth less than 2 kHz, low phase noise, low relative intensity noise (RIN), and high immunity to vibrations in a wide range of operating temperatures.

Posted in: Application Briefs, Lasers & Laser Systems, Semiconductors & ICs, Lidar, Lidar, Suppliers, Semiconductors
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Interface Supports Multiple Broadcast Transceivers for Flight Applications

A wireless avionics interface provides a mechanism for managing multiple broadcast transceivers. This interface isolates the control logic required to support multiple transceivers so that the flight application does not have to manage wireless transceivers. All of the logic to select transceivers, detect transmitter and receiver faults, and take autonomous recovery action is contained in the interface, which is not restricted to using wireless transceivers. Wired, wireless, and mixed transceiver technologies are supported.

Posted in: Briefs, Semiconductors & ICs, Avionics, Data exchange, Integrated circuits, Wireless communication systems, Avionics, Data exchange, Integrated circuits, Wireless communication systems
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FPGA Sequencer for Radar Altimeter Applications

A sequencer for a radar altimeter provides accurate attitude information for a reliable soft landing of the Mars Science Laboratory (MSL). This is a field-programmable-gate-array (FPGA)-only implementation. A table loaded externally into the FPGA controls timing, processing, and decision structures. Radar is memory-less and does not use previous acquisitions to assist in the current acquisition. All cycles complete in exactly 50 milliseconds, regardless of range or whether a target was found.

Posted in: Briefs, Semiconductors & ICs, Altimeters, Attitude control, Integrated circuits, Radar, Spacecraft guidance, Altimeters, Attitude control, Integrated circuits, Radar, Spacecraft guidance, Entry, descent, and landing
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SAD5 Stereo Correlation Line-Striping in an FPGA

High precision SAD5 stereo computations can be performed in an FPGA (field-programmable gate array) at much higher speeds than possible in a conventional CPU (central processing unit), but this uses large amounts of FPGA resources that scale with image size. Of the two key resources in an FPGA, Slices and BRAM (block RAM), Slices scale linearly in the new algorithm with image size, and BRAM scales quadratically with image size. An approach was developed to trade latency for BRAM by sub-windowing the image vertically into overlapping strips and stitching the outputs together to create a single continuous disparity output.

Posted in: Briefs, TSP, Semiconductors & ICs, Mathematical models, Antennas, Architecture, Integrated circuits, Antennas, Architecture, Integrated circuits
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Miniature Sapphire Acoustic Resonator — MSAR

Q values as high as 108 may be achieved at room temperature.

A room temperature sapphire acoustics resonator incorporated into an oscillator represents a possible opportunity to improve on quartz ultrastable oscillator (USO) performance, which has been a staple for NASA missions since the inception of spaceflight. Where quartz technology is very mature and shows a performance improvement of perhaps 1 dB/decade, these sapphire acoustic resonators when integrated with matured quartz electronics could achieve a frequency stability improvement of 10 dB or more. As quartz oscillators are an essential element of nearly all types of frequency standards and reference systems, the success of MSAR would advance the development of frequency standards and systems for both ground-based and flight-based projects.

Posted in: Briefs, Semiconductors & ICs, Product development, Standardization, Semiconductors, Acoustics, Acoustics
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Process-Hardened, Multi-Analyte Sensor for Characterizing Rocket Plume Constituents

A multi-analyte sensor was developed that enables simultaneous detection of rocket engine combustion-product molecules in a launch-vehicle ground test stand. The sensor was developed using a pin-printing method by incorporating multiple sensor elements on a single chip. It demonstrated accurate and sensitive detection of analytes such as carbon dioxide, carbon monoxide, kerosene, isopropanol, and ethylene from a single measurement.

Posted in: Briefs, Semiconductors & ICs, Integrated circuits, Sensors and actuators, Integrated circuits, Sensors and actuators, Emissions measurement, Semiconductors, Rocket engines
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