Tech Briefs

Output power exceeds that of prior solid-state amplifiers operating above 110 GHz.

One of the challenges in designing MMIC power amplifiers to operate above W-band is the choice of transistor. InP HEMTs having gate lengths no larger than 0.12 μm are the most mature technology available, though InP double- heterojunction bipolar transistors are starting to gain ground. A second challenge is to powercombine as many large-periphery transistors as possible within the constraints of matching networks at the higher frequencies. The best W-band power amplifiers utilize eight-way power combiners for a total gate periphery of 1.2 mm. Since powercombining field-effect transistors (FETs) involves placing source vias between the FETs, the compactness of power-combining structures becomes more difficult as wavelength decreases. One result of the constraints imposed by design rules, fabrication processes, and current-carrying capacities of the transmission line circuit elements, is that the range of coplanar-waveguide impedances available for matching networks is restricted approximately to between 23 and 65 Ω.

The present two MMIC amplifier chips were designed with these challenges and constraints in mind. The transistors on these chips are 0.11- μm-gate-length AlInAs/GaInAs/InP HEMT devices grown by molecularbeam epitaxy at HRL Laboratories, LLC. These transistors exhibit typical DC transconductances of 1,050 mS/mm and breakdown voltages of 4 V. The transistors include four gate fingers, each 37 μm wide, making a total periphery of 148 μm. The circuitry is formed using a grounded coplanar-waveguide transmission lines on a 50-μm-thick InP substrate. Vias between the top ground planes and back-side metal are used to suppress unwanted substrate waveguide modes. The chip shown in the upper part of the figure incorporates three stages. The final stage contains two powercombined HEMTs, so that the total gate periphery of the output stage is about 300 μm. The chip shown in the lower part of the figure incorporates three stages. The final stage on this chip contains a fourway power combiner at the output; hence, the total gate periphery of the output stage of this chip is about 600 μm. The amplifier chips were mounted in waveguide modules. When tested, these amplifier modules exhibited gains of 15 to 20 dB and output powers from 20 to 45 mW — the highest output powers thus far obtained from any solid-state amplifier modules above 110 GHz.

This work was done by Lorene Samoska, David Pukala, and Alejandro Peralta of Caltech for NASA’s Jet Propulsion Laboratory; Eric Bryerton, Matt Morgan, and T. Boyd of the National Radio Astronomy Observatory; and Ming Hu and Adele Schmitz of HRL Laboratories, LLC.

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